T2 ITBlock: add support for Windows specific relocation handling

[abdulras]

Summary

This fixes the handling of mov.w/mov.t relocations (IMAGE_REL_ARM_MOV32T) that
cannot be split up. This occurs in a very specific case of two chained IT
blocks with the load of an address being placed in the third slot (position 4).
Because IT blocks may contain 1-4 instructions, and the load is a pair of
consecutive instructions, placement into slot 3 causes a spill into the second
IT block.

The resulting instruction block appears in the following form:

itttt {type}
{dont care}
{dont care}
{dont care}
mov.w {address}
it[ttt] {type}
mov.t {address}
{dont care}
{dont care}
{dont care}

In particular, the problem is that the mov.w/mov.t relocation of the address is
split with a secondary instruction in between them. This is problematic on
Windows, where the IMAGE_REL_ARM_MOV32T relocation cannot be split as the loader
expects that the instructions occur sequentially.

Unfortunately, constructing a test case for this scenario is quite tricky and
extremely fragile, and until a flexible system for running optimisations over
MachineFunctions is implemented, this seems too flaky to construct a test case
for.

[rengolin]

Saleem,

Isn't that the same case as the other movt/movw bug? I think Tim's solution to make them into a block of two instructions will guarantee that they'll never be split on Windows, and make this patch irrelevant.

cheers,
--renato

[abdulras]

I believe that should be correctly handled by the bundling approach (SVN r207608). It can always be resurrected if necessary.

lib/Target/ARM/Thumb2ITBlockPass.cpp

if (I != E) {
     unsigned NPredReg = 0;
     ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg);
     if (NCC == CC || NCC == OCC)
       return true;
   }
   return false;
 }
 
+static bool IsAddress(const MachineOperand &MO) {
+  return MO.isGlobal() || MO.isSymbol() || MO.isCPI();
+}
+
 bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
+  const Triple T(MBB.getParent()->getTarget().getTargetTriple());
   bool Modified = false;
 
   SmallSet<unsigned, 4> Defs;
   SmallSet<unsigned, 4> Uses;
   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
   while (MBBI != E) {
     MachineInstr *MI = &*MBBI;
     DebugLoc dl = MI->getDebugLoc();
if (!restrictIT) {
       for (; MBBI != E && Pos &&
              (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
         if (MBBI->isDebugValue())
           continue;
 
         MachineInstr *NMI = &*MBBI;
         MI = NMI;
 
+        if (T.isOSWindows()) {
+          if (MI->getOpcode() == ARM::t2MOVi16 && IsAddress(MI->getOperand(1))) {
+            assert(MI->getOperand(1).getTargetFlags() == ARMII::MO_LO16 &&
+                   "expected low address load");
+            assert(MBBI != E && "expected hi address load instruction");
+            if (Pos < 2)
+              break;
+          }
+        }
+
         unsigned NPredReg = 0;
         ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg);
         if (NCC == CC || NCC == OCC) {
           Mask |= (NCC & 1) << Pos;
           // Add implicit use of ITSTATE.
           NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
                                                  true/*isImp*/, false/*isKill*/));
           LastITMI = NMI;