Fix assertion with a trunc store to an i1 vector.

[arsenm]

Summary

The getZeroExtendInReg complains because the type is not a scalar.
This only half fixes the problem I ran into, since it ends up creating
an illegal vector operation, but I don't need this anymore.

[arsenm]

Fix other assert in ShrinkDemandedOp. It might be better to just fully disable it for vectors, since it seems unlikely that isTruncateFree or isZExtFree would be true for any vectors

[arsenm]

Ping

[arsenm]

Ping

[arsenm]

Ping

[qcolombet]

Testcase?

[arsenm]

Add testcase that doesn't hit the assertion anymore. It's not particularly useful though, since this introduces an illegal vector operation which fails to select. I'm not sure exactly what i1 vector stores are supposed to do, so I'm not sure how to fix that part.

[qcolombet]

IIRC the semantic of Y x i1 is a packed vector of bool. I.e., you just need Y bits to hold the whole vector. This matches the AVX-512 vector mask.
That said, I do not find the thread discussing that and may be wrong.

Adding Nadav and Hal may be a good idea.

-Quentin

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

         // Promote to a byte-sized store with upper bits zero if not
         // storing an integral number of bytes.  For example, promote
         // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
+
+        EVT ScalarStVT = StVT.getScalarType();
         EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
-                                    StVT.getStoreSizeInBits());
-        Value = DAG.getZeroExtendInReg(Value, dl, StVT);
+                                    ScalarStVT.getStoreSizeInBits());
+        if (StVT.isVector()) {
+          NVT = EVT::getVectorVT(*DAG.getContext(), NVT,
+                                 StVT.getVectorNumElements());
+        }
+
+        Value = DAG.getZeroExtendInReg(Value, dl, ScalarStVT);
         SDValue Result =
           DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
                             NVT, isVolatile, isNonTemporal, Alignment,

lib/CodeGen/SelectionDAG/TargetLowering.cpp

   unsigned SmallVTBits = DemandedSize;
   if (!isPowerOf2_32(SmallVTBits))
     SmallVTBits = NextPowerOf2(SmallVTBits);
+
+  EVT VT = Op.getValueType();
+  unsigned NElts = VT.isVector() ? VT.getVectorNumElements() : 0;
   for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
     EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
+    if (NElts != 0)
+      SmallVT = EVT::getVectorVT(*DAG.getContext(), SmallVT, NElts);
+
     if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
         TLI.isZExtFree(SmallVT, Op.getValueType())) {
       // We found a type with free casts.

test/CodeGen/R600/trunc-store-i1-vector.ll

+; XFAIL: *
+; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+
+; SI-LABEL: @global_truncstore_v4i32_to_v4i1
+define void @global_truncstore_v4i32_to_v4i1(<4 x i1> addrspace(1)* %out, <4 x i32> %val) nounwind {
+  %trunc = trunc <4 x i32> %val to <4 x i1>
+  store <4 x i1> %trunc, <4 x i1> addrspace(1)* %out
+  ret void
+}