[X86][MS-compatability]Allow named synonymous for MS-assembly operators

[coby]

Summary

This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability
MASM reference:
https://msdn.microsoft.com/en-us/library/94b6khh4.aspx

[myatsina]

lib/Target/X86/AsmParser/X86AsmParser.cpp

685 ↗

(On Diff #92760)

I don't think it should be part of the state machine. I think this function should move to the parser and be activates as part of ParseIntelExpression.

test/MC/X86/intel-syntax-bitwise-ops.s

9 ↗

(On Diff #92760)

It seems you have a space instead of a tab in all the checks

42 ↗

(On Diff #92760)

Add a few tests for the upper case as well (AND, OR).
Add some complex case like "(6 and 3) XOR 9"

[coby]

Addressed Marina's comments

[rnk]

Nice, looks good.

llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp

private:
   std::unique_ptr<X86Operand> ParseIntelOperand();
   std::unique_ptr<X86Operand> ParseIntelOffsetOfOperator();
   bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp);
   unsigned IdentifyIntelOperator(StringRef Name);
   unsigned ParseIntelOperator(unsigned OpKind);
   std::unique_ptr<X86Operand>
   ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size);
   std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start, SMLoc End);
+  bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM);
   bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
   std::unique_ptr<X86Operand>
   ParseIntelBracExpression(unsigned SegReg, SMLoc Start, int64_t ImmDisp,
                            bool isSymbol, unsigned Size);
   bool ParseIntelIdentifier(const MCExpr *&Val, StringRef &Identifier,
                             InlineAsmIdentifierInfo &Info,
                             bool IsUnevaluatedOperand, SMLoc &End);
 
RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> &AsmRewrites,
   // Skip everything after the symbol.
   if (unsigned Len = End.getPointer() - (SymLocPtr + SymName.size())) {
     SMLoc Loc = SMLoc::getFromPointer(SymLocPtr + SymName.size());
     assert(Len > 0 && "Expected a non-negative length.");
     AsmRewrites.emplace_back(AOK_Skip, Loc, Len);
   }
 }
 
+// Some binary bitwise operators have a named synonymous
+// Query a candidate string for being such a named operator
+// and if so - invoke the appropriate handler
+bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) {
+  // A named operator should be either lower or upper case, but not a mix
+  if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
+    return false;
+  if (Name.equals_lower("not"))
+    SM.onNot();
+  else if (Name.equals_lower("or"))
+    SM.onOr();
+  else if (Name.equals_lower("shl"))
+    SM.onLShift();
+  else if (Name.equals_lower("shr"))
+    SM.onRShift();
+  else if (Name.equals_lower("xor"))
+    SM.onXor();
+  else if (Name.equals_lower("and"))
+    SM.onAnd();
+  else
+    return false;
+  return true;
+}
+
 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
   MCAsmParser &Parser = getParser();
   const AsmToken &Tok = Parser.getTok();
 
   AsmToken::TokenKind PrevTK = AsmToken::Error;
   bool Done = false;
   while (!Done) {
     bool UpdateLocLex = true;
case AsmToken::Identifier: {
       // This could be a register or a symbolic displacement.
       unsigned TmpReg;
       const MCExpr *Val;
       SMLoc IdentLoc = Tok.getLoc();
       StringRef Identifier = Tok.getString();
       UpdateLocLex = false;
       if (TK != AsmToken::String && !ParseRegister(TmpReg, IdentLoc, End)) {
         SM.onRegister(TmpReg);
+      } else if (ParseIntelNamedOperator(Identifier, SM)) {
+        UpdateLocLex = true;
       } else if (!isParsingInlineAsm()) {
         if (getParser().parsePrimaryExpr(Val, End))
           return Error(Tok.getLoc(), "Unexpected identifier!");
         SM.onIdentifierExpr(Val, Identifier);
       } else if (unsigned OpKind = IdentifyIntelOperator(Identifier)) {
         if (OpKind == IOK_OFFSET) 
           return Error(IdentLoc, "Dealing OFFSET operator as part of"
             "a compound immediate expression is yet to be supported");

llvm/trunk/test/MC/X86/intel-syntax-bitwise-ops.s

 // RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=att %s | FileCheck %s
 
 .intel_syntax
 
 // CHECK: andl  $3, %ecx
     and ecx, 1+2
 // CHECK: andl  $3, %ecx
     and ecx, 1|2
-// CHECK: andl  $3, %ecx
+// CHECK: andl $3, %ecx
+    and ecx, 1 or 2
+// CHECK: andl $3, %ecx
+    and ecx, 1 OR 2
+// CHECK: andl $3, %ecx
     and ecx, 1*3
 // CHECK: andl  $1, %ecx
     and ecx, 1&3
-// CHECK: andl  $0, %ecx
+// CHECK: andl $1, %ecx
+    and ecx, 1 and 3
+// CHECK: andl $1, %ecx
+    and ecx, 1 AND 3
+// CHECK: andl $0, %ecx
     and ecx, (1&2)
-// CHECK: andl  $3, %ecx
+// CHECK: andl $0, %ecx
+    and ecx, (1 and 2)
+// CHECK: andl $0, %ecx
+    and ecx, (1 AND 2)
+// CHECK: andl $3, %ecx
     and ecx, ((1)|2)
-// CHECK: andl  $1, %ecx
+// CHECK: andl $3, %ecx
+    and ecx, ((1) or 2)
+// CHECK: andl $3, %ecx
+    and ecx, ((1) OR 2)
+// CHECK: andl $1, %ecx
     and ecx, 1&2+3
-// CHECK: addl  $4938, %eax
+// CHECK: andl $1, %ecx
+    and ecx, 1 and 2+3
+// CHECK: andl $1, %ecx
+    and ecx, 1 AND 2+3
+// CHECK: addl $4938, %eax
     add eax, 9876 >> 1
-// CHECK: addl  $19752, %eax
+// CHECK: addl $4938, %eax
+    add eax, 9876 shr 1
+// CHECK: addl $4938, %eax
+    add eax, 9876 SHR 1
+// CHECK: addl $19752, %eax
     add eax, 9876 << 1
-// CHECK: addl  $5, %eax
+// CHECK: addl $19752, %eax
+    add eax, 9876 shl 1
+// CHECK: addl $19752, %eax
+    add eax, 9876 SHL 1
+// CHECK: addl $5, %eax
     add eax, 6 ^ 3
+// CHECK: addl $5, %eax
+    add eax, 6 xor 3
+// CHECK: addl $5, %eax
+    add eax, 6 XOR 3
+// CHECK: addl $5, %eax
+    add eax, 6 XOR 3 shl 1 SHR 1