This patch adds NaCl target for Mips. It also forbids indexed loads and stores if the target is NaCl.
Details
Diff Detail
Event Timeline
lib/Target/Mips/MipsInstrFPU.td | ||
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393 | It might be worth commenting why these instructions are disallowed under NaCl -- either in the code or at least in the commit message -- because I don't actually know why they are. Are these inherently dangerous, or is it just that they haven't been added to the MIPS validator's whitelist yet? | |
lib/Target/Mips/MipsInstrInfo.td | ||
190 | Nit: You don't actually use this yet, so you could leave it out | |
lib/Target/Mips/MipsSubtarget.h | ||
212 | This one isn't used. |
lib/Target/Mips/MipsInstrFPU.td | ||
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393 |
Similar to ARM, register-indexed addressing is not supported by design in MIPS NaCl. |
lib/Target/Mips/MipsInstrFPU.td | ||
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393 | OK, I see. Is it the "x" in the instruction name that indicates this addressing mode? Which part of the tablegen definition indicates this addressing mode? Maybe comment something like: |
lib/Target/Mips/MipsInstrFPU.td | ||
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393 |
All indexed loads and stores derive from tablegen classes LWXC1_FT and SWXC1_FT where base and offset are defined to have type PtrRC (or ptr_rc), which represents, if I understand correctly, a pointer value operand whose register class is resolved by using the TargetRegisterInfo::getPointerRegClass() hook at codegen time. |
It might be worth commenting why these instructions are disallowed under NaCl -- either in the code or at least in the commit message -- because I don't actually know why they are.
Are these inherently dangerous, or is it just that they haven't been added to the MIPS validator's whitelist yet?