Add NaCl target for Mips. Forbid indexed loads and stores if the target is NaCl.

[sstankovic]

Summary

This patch adds NaCl target for Mips. It also forbids indexed loads and stores if the target is NaCl.

[mseaborn]

lib/Target/Mips/MipsInstrFPU.td

393 ↗

(On Diff #6858)

It might be worth commenting why these instructions are disallowed under NaCl -- either in the code or at least in the commit message -- because I don't actually know why they are.

Are these inherently dangerous, or is it just that they haven't been added to the MIPS validator's whitelist yet?

lib/Target/Mips/MipsInstrInfo.td

190 ↗

(On Diff #6858)

Nit: You don't actually use this yet, so you could leave it out

lib/Target/Mips/MipsSubtarget.h

212 ↗

(On Diff #6858)

This one isn't used.

[petarj]

lib/Target/Mips/MipsInstrFPU.td

393 ↗

(On Diff #6858)

Are these inherently dangerous, or is it just that they haven't been added to the MIPS validator's whitelist yet?

Similar to ARM, register-indexed addressing is not supported by design in MIPS NaCl.

[mseaborn]

lib/Target/Mips/MipsInstrFPU.td

393 ↗

(On Diff #6858)

OK, I see. Is it the "x" in the instruction name that indicates this addressing mode? Which part of the tablegen definition indicates this addressing mode?

Maybe comment something like:
'"x" indicates a base register + offset register addressing mode which is disallowed under NaCl'

[sstankovic]

lib/Target/Mips/MipsInstrFPU.td

393 ↗

(On Diff #6858)

Which part of the tablegen definition indicates this addressing mode?

All indexed loads and stores derive from tablegen classes LWXC1_FT and SWXC1_FT where base and offset are defined to have type PtrRC (or ptr_rc), which represents, if I understand correctly, a pointer value operand whose register class is resolved by using the TargetRegisterInfo::getPointerRegClass() hook at codegen time.

[sstankovic]

Patch is updated.

[mseaborn]

LGTM, thanks

[petarj]

Closed by commit rL200855 (authored by @petarj).

llvm/trunk/lib/Target/Mips/MipsInstrFPU.td

 let Predicates = [HasStdEnc] in {
   def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>;
   def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>;
   def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>;
   def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>;
 }
 
 // Indexed loads and stores.
-let Predicates = [HasFPIdx, HasStdEnc] in {
+// Base register + offset register addressing mode (indicated by "x" in the
+// instruction mnemonic) is disallowed under NaCl.
+let Predicates = [HasFPIdx, HasStdEnc, IsNotNaCl] in {
   def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>;
   def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>;
 }
 
-let Predicates = [HasFPIdx, NotFP64bit, HasStdEnc, NotInMicroMips] in {
+let Predicates = [HasFPIdx, NotFP64bit, HasStdEnc, NotInMicroMips,
+                  IsNotNaCl] in {
   def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
   def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
 }
 
 let Predicates = [HasFPIdx, IsFP64bit, HasStdEnc],
     DecoderNamespace="Mips64" in {
   def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
   def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
 }
 
 // Load/store doubleword indexed unaligned.
-let Predicates = [NotFP64bit, HasStdEnc] in {
+let Predicates = [NotFP64bit, HasStdEnc, IsNotNaCl] in {
   def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
   def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
 }
 
 let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace="Mips64" in {
   def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
   def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
 }

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

def HasStdEnc :       Predicate<"Subtarget.hasStandardEncoding()">,
                       AssemblerPredicate<"!FeatureMips16">;
 def NotDSP :          Predicate<"!Subtarget.hasDSP()">;
 def InMicroMips    :  Predicate<"Subtarget.inMicroMipsMode()">,
                       AssemblerPredicate<"FeatureMicroMips">;
 def NotInMicroMips :  Predicate<"!Subtarget.inMicroMipsMode()">,
                       AssemblerPredicate<"!FeatureMicroMips">;
 def IsLE           :  Predicate<"Subtarget.isLittle()">;
 def IsBE           :  Predicate<"!Subtarget.isLittle()">;
+def IsNotNaCl    :    Predicate<"!Subtarget.isTargetNaCl()">;
 
 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
   let Predicates = [HasStdEnc];
 }
 
 class IsCommutable {
   bit isCommutable = 1;
 }

llvm/trunk/lib/Target/Mips/MipsSubtarget.h

protected:
   Reloc::Model RM;
 
   // We can override the determination of whether we are in mips16 mode
   // as from the command line
   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
 
   MipsTargetMachine *TM;
 
+  Triple TargetTriple;
 public:
   virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
                                      AntiDepBreakMode& Mode,
                                      RegClassVector& CriticalPathRCs) const;
 
   /// Only O32 and EABI supported right now.
   bool isABI_EABI() const { return MipsABI == EABI; }
   bool isABI_N64() const { return MipsABI == N64; }
public:
   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
 
   const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
   bool allowMixed16_32() const { return inMips16ModeDefault() |
                                         AllowMixed16_32;}
 
   bool os16() const { return Os16;};
 
+  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
+
 // for now constant islands are on for the whole compilation unit but we only
 // really use them if in addition we are in mips16 mode
 //
 static bool useConstantIslands();
 
   unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
 
   // Grab relocation model

llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp

MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
   MipsGenSubtargetInfo(TT, CPU, FS),
   MipsArchVersion(Mips32), MipsABI(UnknownABI), IsLittle(little),
   IsSingleFloat(false), IsFP64bit(false), IsGP64bit(false), HasVFPU(false),
   IsLinux(true), HasSEInReg(false), HasCondMov(false), HasSwap(false),
   HasBitCount(false), HasFPIdx(false),
   InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
   InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
   AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
-  RM(_RM), OverrideMode(NoOverride), TM(_TM)
+  RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT)
 {
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = "mips32";
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);
 

llvm/trunk/test/CodeGen/Mips/fp-indexed-ls.ll

 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s \
+; RUN:  | FileCheck %s -check-prefix=CHECK-NACL
 
 %struct.S = type <{ [4 x float] }>
 %struct.S2 = type <{ [4 x double] }>
 %struct.S3 = type <{ i8, float }>
 
 @s = external global [4 x %struct.S]
 @gf = external global float
 @gd = external global double
 @s2 = external global [4 x %struct.S2]
 @s3 = external global %struct.S3
 
 define float @foo0(float* nocapture %b, i32 %o) nounwind readonly {
 entry:
 ; CHECK: lwxc1
+; CHECK-NACL-NOT: lwxc1
   %arrayidx = getelementptr inbounds float* %b, i32 %o
   %0 = load float* %arrayidx, align 4
   ret float %0
 }
 
 define double @foo1(double* nocapture %b, i32 %o) nounwind readonly {
 entry:
 ; CHECK: ldxc1
+; CHECK-NACL-NOT: ldxc1
   %arrayidx = getelementptr inbounds double* %b, i32 %o
   %0 = load double* %arrayidx, align 8
   ret double %0
 }
 
 define float @foo2(i32 %b, i32 %c) nounwind readonly {
 entry:
 ; CHECK-NOT: luxc1
   %arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
   %0 = load float* %arrayidx1, align 1
   ret float %0
 }
 
 define void @foo3(float* nocapture %b, i32 %o) nounwind {
 entry:
 ; CHECK: swxc1
+; CHECK-NACL-NOT: swxc1
   %0 = load float* @gf, align 4
   %arrayidx = getelementptr inbounds float* %b, i32 %o
   store float %0, float* %arrayidx, align 4
   ret void
 }
 
 define void @foo4(double* nocapture %b, i32 %o) nounwind {
 entry:
 ; CHECK: sdxc1
+; CHECK-NACL-NOT: sdxc1
   %0 = load double* @gd, align 8
   %arrayidx = getelementptr inbounds double* %b, i32 %o
   store double %0, double* %arrayidx, align 8
   ret void
 }
 
 define void @foo5(i32 %b, i32 %c) nounwind {
 entry: