AMDGPU/R600: Remove intrinsics with no tests and no users

[arsenm]

Summary

Mesa removed this path, so nothing is using these anymore.

[• tstellarAMD]

LGTM.

[arsenm]

r275372

lib/Target/AMDGPU/AMDGPUInstructions.td

 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains instruction defs that are common to all hw codegen
 // targets.
 //
 //===----------------------------------------------------------------------===//
 
-class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
+class AMDGPUInst <dag outs, dag ins, string asm = "",
+  list<dag> pattern = []> : Instruction {
   field bit isRegisterLoad = 0;
   field bit isRegisterStore = 0;
 
   let Namespace = "AMDGPU";
   let OutOperandList = outs;
   let InOperandList = ins;
   let AsmString = asm;
   let Pattern = pattern;
   let Itinerary = NullALU;
 
   // SoftFail is a field the disassembler can use to provide a way for
   // instructions to not match without killing the whole decode process. It is
   // mainly used for ARM, but Tablegen expects this field to exist or it fails
   // to build the decode table.
   field bits<64> SoftFail = 0;
 
   let DecoderNamespace = Namespace;
 
   let TSFlags{63} = isRegisterLoad;
   let TSFlags{62} = isRegisterStore;
 }
 
-class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
-    : AMDGPUInst<outs, ins, asm, pattern> {
+class AMDGPUShaderInst <dag outs, dag ins, string asm = "",
+  list<dag> pattern = []> : AMDGPUInst<outs, ins, asm, pattern> {
 
   field bits<32> Inst = 0xffffffff;
-
 }
 
 def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">;
 def FP64Denormals : Predicate<"Subtarget.hasFP64Denormals()">;
 def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
 
 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;

lib/Target/AMDGPU/R600ISelLowering.cpp

SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   }
   case ISD::INTRINSIC_WO_CHAIN: {
     unsigned IntrinsicID =
                          cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
     EVT VT = Op.getValueType();
     SDLoc DL(Op);
     switch(IntrinsicID) {
     default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
-    case AMDGPUIntrinsic::R600_interp_xy:
-    case AMDGPUIntrinsic::R600_interp_zw: {
-      int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
-      MachineSDNode *interp;
-      SDValue RegisterINode = Op.getOperand(2);
-      SDValue RegisterJNode = Op.getOperand(3);
-
-      if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
-        interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
-            MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32),
-            RegisterJNode, RegisterINode);
-      else
-        interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
-            MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32),
-            RegisterJNode, RegisterINode);
-      return DAG.getBuildVector(MVT::v2f32, DL,
-                                {SDValue(interp, 0), SDValue(interp, 1)});
-    }
     case AMDGPUIntrinsic::r600_tex:
     case AMDGPUIntrinsic::r600_texc:
     case AMDGPUIntrinsic::r600_txl:
     case AMDGPUIntrinsic::r600_txlc:
     case AMDGPUIntrinsic::r600_txb:
     case AMDGPUIntrinsic::r600_txbc:
     case AMDGPUIntrinsic::r600_txf:
     case AMDGPUIntrinsic::r600_txq:
     case AMDGPUIntrinsic::r600_ddx:
-    case AMDGPUIntrinsic::r600_ddy:
-    case AMDGPUIntrinsic::R600_ldptr: {
+    case AMDGPUIntrinsic::r600_ddy: {
       unsigned TextureOp;
       switch (IntrinsicID) {
       case AMDGPUIntrinsic::r600_tex:
         TextureOp = 0;
         break;
       case AMDGPUIntrinsic::r600_texc:
         TextureOp = 1;
         break;
case AMDGPUIntrinsic::r600_ddy: {
         TextureOp = 7;
         break;
       case AMDGPUIntrinsic::r600_ddx:
         TextureOp = 8;
         break;
       case AMDGPUIntrinsic::r600_ddy:
         TextureOp = 9;
         break;
-      case AMDGPUIntrinsic::R600_ldptr:
-        TextureOp = 10;
-        break;
       default:
         llvm_unreachable("Unknow Texture Operation");
       }
 
       SDValue TexArgs[19] = {
         DAG.getConstant(TextureOp, DL, MVT::i32),
         Op.getOperand(1),
         DAG.getConstant(0, DL, MVT::i32),

lib/Target/AMDGPU/R600Instructions.td

 // TableGen definitions for instructions which are available on R600 family
 // GPUs.
 //
 //===----------------------------------------------------------------------===//
 
 include "R600Intrinsics.td"
 include "R600InstrFormats.td"
 
-class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
+class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern = []> :
     InstR600 <outs, ins, asm, pattern, NullALU> {
 
   let Namespace = "AMDGPU";
 }
 
 def MEMxi : Operand<iPTR> {
   let MIOperandInfo = (ops R600_TReg32_X:$ptr, i32imm:$index);
   let PrintMethod = "printMemOperand";

 
 //===----------------------------------------------------------------------===//
 // Interpolation Instructions
 //===----------------------------------------------------------------------===//
 
 def INTERP_VEC_LOAD :  AMDGPUShaderInst <
   (outs R600_Reg128:$dst),
   (ins i32imm:$src0),
-  "INTERP_LOAD $src0 : $dst",
-  [(set R600_Reg128:$dst, (int_R600_interp_const imm:$src0))]>;
+  "INTERP_LOAD $src0 : $dst">;
 
 def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []> {
   let bank_swizzle = 5;
 }
 
 def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []> {
   let bank_swizzle = 5;
 }
class ExportBufWord1 {
   bits<1> eop;
   bits<8> inst;
 
   let Word1{11-0} = arraySize;
   let Word1{15-12} = compMask;
 }
 
 multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
-  def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
-    (ExportInst
-        (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
-        0, 61, 0, 7, 7, 7, cf_inst, 0)
-  >;
-
-  def : Pat<(int_R600_store_pixel_stencil R600_Reg32:$reg),
-    (ExportInst
-        (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
-        0, 61, 7, 0, 7, 7, cf_inst, 0)
-  >;
-
-  def : Pat<(int_R600_store_dummy (i32 imm:$type)),
-    (ExportInst
-        (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
-  >;
-
-  def : Pat<(int_R600_store_dummy 1),
-    (ExportInst
-        (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
-  >;
-
   def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
     (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
         (ExportInst R600_Reg128:$src, imm:$type, imm:$base,
         imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
   >;
 
 }
 

 
 // VTX_WORD3 (Padding)
 //
 // Inst{127-96} = 0;
   let VTXInst = 1;
 }
 
 def TEX_VTX_TEXBUF:
-  InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr",
-      [(set v4f32:$dst, (int_R600_load_texbuf ADDRGA_VAR_OFFSET:$ptr, imm:$BUFFER_ID))]>,
+  InstR600ISA <(outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), "TEX_VTX_EXPLICIT_READ $dst, $ptr">,
 VTX_WORD1_GPR, VTX_WORD0_eg {
 
 let VC_INST = 0;
 let FETCH_TYPE = 2;
 let FETCH_WHOLE_QUAD = 0;
 let SRC_REL = 0;
 let SRC_SEL_X = 0;
 let DST_REL = 0;

lib/Target/AMDGPU/R600Intrinsics.td

 //===-- R600Intrinsics.td - R600 Instrinsic defs -------*- tablegen -*-----===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // R600 Intrinsic Definitions
 //
 //===----------------------------------------------------------------------===//
 
 // FIXME: Should migrate to using TargetPrefix that matches triple arch name.
 let TargetPrefix = "R600", isTarget = 1 in {
+  def int_R600_store_swizzle :
+    Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
+  def int_R600_store_stream_output :
+    Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
+} // End TargetPrefix = "R600", isTarget = 1
+
+let TargetPrefix = "r600", isTarget = 1 in {
   class TextureIntrinsicFloatInput :
     Intrinsic<[llvm_v4f32_ty], [
       llvm_v4f32_ty, // Coord
       llvm_i32_ty, // offset_x
       llvm_i32_ty, // offset_y,
       llvm_i32_ty, // offset_z,
       llvm_i32_ty, // resource_id
       llvm_i32_ty, // samplerid
Intrinsic<[llvm_v4i32_ty], [
       llvm_i32_ty, // resource_id
       llvm_i32_ty, // samplerid
       llvm_i32_ty, // coord_type_x
       llvm_i32_ty, // coord_type_y
       llvm_i32_ty, // coord_type_z
       llvm_i32_ty // coord_type_w
     ], [IntrNoMem]>;
 
-  def int_R600_ldptr : TextureIntrinsicInt32Input;
 
-  def int_R600_interp_const :
-    Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], [IntrNoMem]>;
-  def int_R600_interp_xy :
-    Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
-  def int_R600_interp_zw :
-    Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
-  def int_R600_load_texbuf :
-    Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
-  def int_R600_store_swizzle :
-    Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
-  def int_R600_store_stream_output :
-    Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
-  def int_R600_store_pixel_depth :
-      Intrinsic<[], [llvm_float_ty], []>;
-  def int_R600_store_pixel_stencil :
-      Intrinsic<[], [llvm_float_ty], []>;
-  def int_R600_store_dummy :
-      Intrinsic<[], [llvm_i32_ty], []>;
-} // End TargetPrefix = "R600", isTarget = 1
-
-let TargetPrefix = "r600", isTarget = 1 in {
   def int_r600_tex : TextureIntrinsicFloatInput;
   def int_r600_texc : TextureIntrinsicFloatInput;
   def int_r600_txl : TextureIntrinsicFloatInput;
   def int_r600_txlc : TextureIntrinsicFloatInput;
   def int_r600_txb : TextureIntrinsicFloatInput;
   def int_r600_txbc : TextureIntrinsicFloatInput;
   def int_r600_txf : TextureIntrinsicInt32Input;
   def int_r600_txq : TextureIntrinsicInt32Input;
   def int_r600_ddx : TextureIntrinsicFloatInput;
   def int_r600_ddy : TextureIntrinsicFloatInput;
 
   def int_r600_dot4 : Intrinsic<[llvm_float_ty],
     [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]
   >;
 } // End TargetPrefix = "r600", isTarget = 1