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Differential D22145

AMDGPU: Simplify isSchedulingBoundary
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Authored by arsenm on Jul 8 2016, 11:20 AM.

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• tstellarAMD

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arsenm updated this revision to Diff 63265.Jul 8 2016, 11:20 AM
arsenm retitled this revision from to AMDGPU: Simplify isSchedulingBoundary.
arsenm updated this object.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: • tstellarAMD. · View Herald TranscriptJul 8 2016, 11:20 AM
Herald added subscribers: kzhuravl, arsenm. · View Herald Transcript
• tstellarAMD accepted this revision.Jul 8 2016, 6:00 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Jul 8 2016, 6:00 PM
arsenm closed this revision.Jul 8 2016, 6:21 PM

r274953

Revision Contents

PathSize
lib/
Target/
AMDGPU/
9 lines

Diff 63265

lib/Target/AMDGPU/SIInstrInfo.cpp

Show First 20 Lines • Show All 1,449 Lines • ▼ Show 20 Lines return BuildMI(*MBB, MI, MI.getDebugLoc(), get(AMDGPU::V_MAD_F32))
.addOperand(*Src2) .addOperand(*Src2)
.addImm(0) // clamp .addImm(0) // clamp
.addImm(0); // omod .addImm(0); // omod
} }
bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI, bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
const MachineBasicBlock *MBB, const MachineBasicBlock *MBB,
const MachineFunction &MF) const { const MachineFunction &MF) const {
// XXX - Do we want the SP check in the base implementation?
// Target-independent instructions do not have an implicit-use of EXEC, even // Target-independent instructions do not have an implicit-use of EXEC, even
// when they operate on VGPRs. Treating EXEC modifications as scheduling // when they operate on VGPRs. Treating EXEC modifications as scheduling
// boundaries prevents incorrect movements of such instructions. // boundaries prevents incorrect movements of such instructions.
const SIRegisterInfo *TRI = MF.getSubtarget<SISubtarget>().getRegisterInfo(); return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF) ||
if (MI.modifiesRegister(AMDGPU::EXEC, TRI)) MI.modifiesRegister(AMDGPU::EXEC, &RI);
return true;
return AMDGPUInstrInfo::isSchedulingBoundary(MI, MBB, MF);
} }
bool SIInstrInfo::isInlineConstant(const APInt &Imm) const { bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
int64_t SVal = Imm.getSExtValue(); int64_t SVal = Imm.getSExtValue();
if (SVal >= -16 && SVal <= 64) if (SVal >= -16 && SVal <= 64)
return true; return true;
if (Imm.getBitWidth() == 64) { if (Imm.getBitWidth() == 64) {
▲ Show 20 Lines • Show All 1,708 Lines • Show Last 20 Lines