[AMDGPU][llvm-mc] Quickfix for r272748 to enable labels in branch instructions.

[artem.tamazov]

Summary

Fixes issue mentioned at:

https://github.com/RadeonOpenCompute/LLVM-AMDGPU-Assembler-Extra/issues/13.

Lit tests added.

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
   case MCK_SSrc32:
     // When operands have expression values, they will return true for isToken,
     // because it is not possible to distinguish between a token and an
     // expression at parse time. MatchInstructionImpl() will always try to
     // match an operand as a token, when isToken returns true, and when the
     // name of the expression is not a valid token, the match will fail,
     // so we need to handle it here.
     return Operand.isSSrc32() ? Match_Success : Match_InvalidOperand;
+  case MCK_SoppBrTarget:
+    return Operand.isSoppBrTarget() ? Match_Success : Match_InvalidOperand;
   default: return Match_InvalidOperand;
   }
 }

llvm/trunk/test/MC/AMDGPU/labels-branch.s

+// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
+
+loop_start:
+s_branch loop_start
+// VI: s_branch loop_start ; encoding: [A,A,0x82,0xbf]
+// VI-NEXT: ;   fixup A - offset: 0, value: loop_start, kind: fixup_si_sopp_br
+
+s_branch loop_end
+// VI: s_branch loop_end ; encoding: [A,A,0x82,0xbf]
+// VI-NEXT: ;   fixup A - offset: 0, value: loop_end, kind: fixup_si_sopp_br
+loop_end:
+
+s_branch gds
+// VI: s_branch gds ; encoding: [A,A,0x82,0xbf]
+// VI-NEXT: ;   fixup A - offset: 0, value: gds, kind: fixup_si_sopp_br
+gds:
+  s_nop 0