Bug 28444: Fix assertion when extract_vector_elt has mismatched type

[arsenm]

Summary

For some reason extract_vector_elt is sometimes allowed to have
a different result type than the vector element type.

[hfinkel]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

12411

Instead of disabling the transformation, you should be able to replace:

return InVec.getOperand(1);

with:

return DAG.getAnyExtOrTrunc(InVec.getOperand(1), SDLoc(N), NVT);

(I double-checked DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT, and it uses an ANY_EXTEND for this case).

[arsenm]

Convert instead of skip

[hfinkel]

LGTM

[arsenm]

r274829

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
   }
 
   // extract_vector_elt (insert_vector_elt vec, val, idx), idx) -> val
   //
   // This only really matters if the index is non-constant since other combines
   // on the constant elements already work.
   if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT &&
       EltNo == InVec.getOperand(2))
-    return InVec.getOperand(1);
+    return DAG.getAnyExtOrTrunc(InVec.getOperand(1), SDLoc(N), NVT);
 
   // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
   // We only perform this optimization before the op legalization phase because
   // we may introduce new vector instructions which are not backed by TD
   // patterns. For example on AVX, extracting elements from a wide vector
   // without using extract_subvector. However, if we can find an underlying
   // scalar value, then we can always use that.
   if (ConstEltNo && InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {

test/CodeGen/X86/pr28444.ll

+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 < %s | FileCheck %s
+; https://llvm.org/bugs/show_bug.cgi?id=28444
+
+; extract_vector_elt is allowed to have a different result type than
+; the vector scalar type.
+; This uses both
+;  i8 = extract_vector_elt v1i1, Constant:i64<0>
+;  i1 = extract_vector_elt v1i1, Constant:i64<0>
+
+
+; CHECK-LABEL: {{^}}extractelt_mismatch_vector_element_type:
+; CHECK: movb $1, %al
+; CHECK: movb %al
+; CHECK: movb %al
+define void @extractelt_mismatch_vector_element_type(i32 %arg) {
+bb:
+  %tmp = icmp ult i32 %arg, 0
+  %tmp2 = insertelement <1 x i1> undef, i1 true, i32 0
+  %tmp3 = select i1 %tmp, <1 x i1> undef, <1 x i1> %tmp2
+  %tmp6 = extractelement <1 x i1> %tmp3, i32 0
+  br label %bb1
+
+bb1:
+  store volatile <1 x i1> %tmp3, <1 x i1>* undef
+  store volatile i1 %tmp6, i1* undef
+  ret void
+}