fix ds_swizzle_b32 opcode for VI (bz 28371)

[vpykhtin]

Summary

This creates the need to use opcode tuple tecnique we used in other instructions.

[arsenm]

lib/Target/AMDGPU/SIInstrInfo.td

2599 ↗

(On Diff #62883)

Why a trailing underscore in the name?

[artem.tamazov]

Shall we take care about DS_1A_RET_ and get rid of TODO. Otherwise, fine.

lib/Target/AMDGPU/SIInstrInfo.td

2599 ↗

(On Diff #62883)

Matt, there is TODO comment about that at line 2612.

2612–2613 ↗

(On Diff #62883)

Perhaps is sensible to remove this class and use dsop everywhere right now. There could be some other similar problems for VI, not yet found for now.

[artem.tamazov]

LGTM if considered as a quickfix. Well... use your <good> judgment, up to you.

[artem.tamazov]

Do not forget to add bugzilla URL to commit description.

[vpykhtin]

lib/Target/AMDGPU/SIInstrInfo.td

2599 ↗

(On Diff #62883)

Matt, its done to distinguish from DS_1A_RET. I agree its better just to replace all usages of DS_1A_RET with dsop operands and remove DS_1A_RET_. On the other hand there're only few differences in ds opcodes between SI and VI.

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

class sop2 <bits<7> si, bits<7> vi = si> {
   field bits<7> VI = vi;
 }
 
 class sopk <bits<5> si, bits<5> vi = si> {
   field bits<5> SI = si;
   field bits<5> VI = vi;
 }
 
+class dsop <bits<8> si, bits<8> vi = si> {
+  field bits<8> SI = si;
+  field bits<8> VI = vi;
+}
+
 // Specify an SMRD opcode for SI and SMEM opcode for VI
 
 // FIXME: This should really be bits<5> si, Tablegen crashes if
 // parameter default value is other parameter with different bit size
 class smrd<bits<8> si, bits<8> vi = si> {
   field bits<5> SI = si{4-0};
   field bits<8> VI = vi;
 }
class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
   DS_Real_vi <op, opName, outs, ins, asm> {
 
   // Single load interpret the 2 i8imm operands as a single i16 offset.
   bits<16> offset;
   let offset0 = offset{7-0};
   let offset1 = offset{15-8};
 }
 
+multiclass DS_1A_RET_ <dsop op, string opName, RegisterClass rc,
+  dag outs = (outs rc:$vdst),
+  dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),
+  string asm = opName#" $vdst, $addr"#"$offset$gds"> {
+
+  def "" : DS_Pseudo <opName, outs, ins, []>;
+
+  let data0 = 0, data1 = 0 in {
+    def _si : DS_Off16_Real_si <op.SI, opName, outs, ins, asm>;
+    def _vi : DS_Off16_Real_vi <op.VI, opName, outs, ins, asm>;
+  }
+}
+
+// TODO: DS_1A_RET can be inherited from DS_1A_RET_ but its not working
+// for some reason. In fact we can remove this class if use dsop everywhere
 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
   dag outs = (outs rc:$vdst),
   dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),
   string asm = opName#" $vdst, $addr"#"$offset$gds"> {
 
   def "" : DS_Pseudo <opName, outs, ins, []>;
 
   let data0 = 0, data1 = 0 in {

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET <
   0x2f, "ds_wrxchg2st64_rtn_b32", VReg_64, "", VGPR_32
 >;
 defm DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
 defm DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
 defm DS_MIN_RTN_F32 : DS_1A2D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
 defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
 
 let Uses = [EXEC], mayLoad =0, mayStore = 0, isConvergent = 1 in {
-defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>;
+defm DS_SWIZZLE_B32 : DS_1A_RET_ <dsop<0x35, 0x3d>, "ds_swizzle_b32", VGPR_32>;
 }
 
 let mayStore = 0 in {
 defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>;
 defm DS_READ2_B32 : DS_1A_Off8_RET <0x37, "ds_read2_b32", VReg_64>;
 defm DS_READ2ST64_B32 : DS_1A_Off8_RET <0x38, "ds_read2st64_b32", VReg_64>;
 defm DS_READ_I8 : DS_1A_RET <0x39, "ds_read_i8", VGPR_32>;
 defm DS_READ_U8 : DS_1A_RET <0x3a, "ds_read_u8", VGPR_32>;

llvm/trunk/test/MC/AMDGPU/ds.s

 // VI:   ds_min_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x64,0xd8,0x02,0x04,0x06,0x08]
 
 ds_max_rtn_f32 v8, v2, v4, v6
 // SICI: ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0xcc,0xd8,0x02,0x04,0x06,0x08]
 // VI:   ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x06,0x08]
 
 ds_swizzle_b32 v8, v2
 // SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
-// VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x08]
+// VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
 
 ds_read_b32 v8, v2
 // SICI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0xd8,0xd8,0x02,0x00,0x00,0x08]
 // VI:   ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08]
 
 ds_read2_b32 v[8:9], v2
 // SICI: ds_read2_b32 v[8:9], v2 ; encoding: [0x00,0x00,0xdc,0xd8,0x02,0x00,0x00,0x08]
 // VI:   ds_read2_b32 v[8:9], v2 ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x08]

llvm/trunk/test/MC/Disassembler/AMDGPU/ds_vi.txt

 0x00 0x00 0x62 0xd8 0x02 0x04 0x06 0x08
 
 # VI:   ds_min_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x64,0xd8,0x02,0x04,0x06,0x08]
 0x00 0x00 0x64 0xd8 0x02 0x04 0x06 0x08
 
 # VI:   ds_max_rtn_f32 v8, v2, v4, v6 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x06,0x08]
 0x00 0x00 0x66 0xd8 0x02 0x04 0x06 0x08
 
-# VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x08]
-0x00 0x00 0x6a 0xd8 0x02 0x00 0x00 0x08
+# VI:   ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
+0x00 0x00 0x7a 0xd8 0x02 0x00 0x00 0x08
 
 # VI:   ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0x6c 0xd8 0x02 0x00 0x00 0x08
 
 # VI:   ds_read2_b32 v[8:9], v2 ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x08]
 0x00 0x00 0x6e 0xd8 0x02 0x00 0x00 0x08
 
 # VI:   ds_read2st64_b32 v[8:9], v2 ; encoding: [0x00,0x00,0x70,0xd8,0x02,0x00,0x00,0x08]