AMDGPU/R600: Fix GlobalValue regressions.

[jvesely]

Summary

Don't cast GV expression to MCSymbolRefExpr. r272705 changed GV to binary
expressions by including offset even if the offset it 0
(we haven't hit this sooner since tested workloads don't include static offsets)
We don't really care about the type of expression, so set it directly.
Fixes: r272705

Consider section relative relocations. Since all const as data is in one buffer section relative is equivalent to abs32.
Fixes: r273166

[jvesely]

remove double semicolon

[• tstellarAMD]

Sorry about breaking this. I guess we can't really add a lit test without assembler support.

[jvesely]

change tests to output object format to test fixups

something like this might work. It detects crashes (and both bugs fixed in this patch) but not much else.
I was unsure about /dev/null, but it looks like the test has used it for some time. We can switch to %t0 if need be

[jvesely]

better tests. use ABS32 for section relative relocs

[• tstellarAMD]

LGTM.

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp

unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
   case MCSymbolRefExpr::VK_GOTPCREL:
     return ELF::R_AMDGPU_GOTPCREL;
   }
 
   switch (Fixup.getKind()) {
   default: break;
   case FK_PCRel_4:
     return ELF::R_AMDGPU_REL32;
+  case FK_SecRel_4:
+    return ELF::R_AMDGPU_ABS32;
   }
 
   llvm_unreachable("unhandled relocation type");
 }
 
 
 MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit,
                                                   bool HasRelocationAddend,
                                                   raw_pwrite_stream &OS) {
   MCELFObjectTargetWriter *MOTW =
       new AMDGPUELFObjectWriter(Is64Bit, HasRelocationAddend);
   return createELFObjectWriter(MOTW, OS, true);
 }

llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp

uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
                                         const MCSubtargetInfo &STI) const {
   if (MO.isReg()) {
     if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
       return MRI.getEncodingValue(MO.getReg());
     return getHWReg(MO.getReg());
   }
 
   if (MO.isExpr()) {
-    const MCSymbolRefExpr *Expr = cast<MCSymbolRefExpr>(MO.getExpr());
     // We put rodata at the end of code section, then map the entire
     // code secetion as vtx buf. Thus the section relative address is the
     // correct one.
     // Each R600 literal instruction has two operands
     // We can't easily get the order of the current one, so compare against
     // the first one and adjust offset.
     const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4;
-    Fixups.push_back(MCFixup::create(offset, Expr, FK_SecRel_4, MI.getLoc()));
+    Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc()));
     return 0;
   }
 
   assert(MO.isImm());
   return MO.getImm();
 }
 
 #include "AMDGPUGenMCCodeEmitter.inc"

llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll

-; RUN: llc -march=amdgcn -mcpu=SI -o /dev/null %s
-; RUN: llc -march=amdgcn -mcpu=tonga -o /dev/null %s
-; RUN: llc -march=r600 -mcpu=cypress -o /dev/null %s
+; RUN: llc -march=amdgcn -mcpu=SI -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN
+; RUN: llc -march=amdgcn -mcpu=tonga -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN
+; RUN: llc -march=r600 -mcpu=cypress -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=EG
 
+; GCN: R_AMDGPU_REL32 extern_const_addrspace
+; EG: R_AMDGPU_ABS32 extern_const_addrspace
+
+; CHECK-DAG: Name: extern_const_addrspace
 @extern_const_addrspace = external unnamed_addr addrspace(2) constant [5 x i32], align 4
 
-; FUNC-LABEL: {{^}}load_extern_const_init:
+; CHECK-DAG: Name: load_extern_const_init
 define void @load_extern_const_init(i32 addrspace(1)* %out) nounwind {
   %val = load i32, i32 addrspace(2)* getelementptr ([5 x i32], [5 x i32] addrspace(2)* @extern_const_addrspace, i64 0, i64 3), align 4
   store i32 %val, i32 addrspace(1)* %out, align 4
   ret void
 }
 
+; CHECK-DAG: Name: undef_const_addrspace
 @undef_const_addrspace = unnamed_addr addrspace(2) constant [5 x i32] undef, align 4
 
-; FUNC-LABEL: {{^}}load_undef_const_init:
+; CHECK-DAG: Name: undef_const_addrspace
 define void @load_undef_const_init(i32 addrspace(1)* %out) nounwind {
   %val = load i32, i32 addrspace(2)* getelementptr ([5 x i32], [5 x i32] addrspace(2)* @undef_const_addrspace, i64 0, i64 3), align 4
   store i32 %val, i32 addrspace(1)* %out, align 4
   ret void
 }