AMDGPU: Added v_mad instruction.

[wdng]

Summary

Added v_mad_16 instruction definition.

[• tstellarAMD]

The commit subject should be be prefixed with AMDGPU:

lib/Target/AMDGPU/VIInstructions.td

78–83 ↗

(On Diff #60788)

Can we also add a pattern and a test with this patch?

[wdng]

This pattern has been tested in LIT test mad_uint24.ll, which is a part of fp16 implementation.

[arsenm]

lib/Target/AMDGPU/VIInstructions.td

82 ↗

(On Diff #60789)

The unsigned version should be also added

281–284 ↗

(On Diff #60789)

This should be left for the i16 patch

[wdng]

Pattern is added for LIT test mad_uint24.ll

[wdng]

lib/Target/AMDGPU/VIInstructions.td

281–284 ↗

(On Diff #60789)

Yes, we may not need the pattern. For this patch, we may only need to add the instruction definition for the time being.

[arsenm]

lib/Target/AMDGPU/VIInstructions.td

281–284 ↗

(On Diff #60789)

The pattern will do nothing here, so yes only the definitions

286 ↗

(On Diff #60789)

This is also trying to use half mul for integer mul

[wdng]

Added v_mad_u16 instruction definition.

[wdng]

lib/Target/AMDGPU/VIInstructions.td

87 ↗

(On Diff #60853)

Could you please say in more details? Thanks!

[arsenm]

The v_mad_f16 instruction is also missing

lib/Target/AMDGPU/VIInstructions.td

82–83 ↗

(On Diff #60853)

These aren't the opcode values I see in the manual

[wdng]

1. Modified opcode for v_mad_u16, v_mad_i16 to make it consistant with the GCN manual.
2. Added v_mad_f16 instruction definition.

[arsenm]

With the capitalization fix LGTM

lib/Target/AMDGPU/VIInstructions.td

82 ↗

(On Diff #60943)

All of the other opcodes use lower case letters in the hex.

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

 def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
 def VOP_F16_I16 : VOPProfile <[f16, i32, untyped, untyped]>;
 def VOP_I16_F16 : VOPProfile <[i32, f16, untyped, untyped]>;
 
 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i32, untyped]>;
 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
 
+def VOP_I16_I16_I16_I16 : VOPProfile <[i32, i32, i32, i32, untyped]>;
+def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
+
 def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
 
 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;

llvm/trunk/lib/Target/AMDGPU/VIInstructions.td

 defm V_MIN_F16 : VOP2Inst <vop2<0,0x2e>, "v_min_f16", VOP_F16_F16_F16>;
 defm V_MAX_U16 : VOP2Inst <vop2<0,0x2f>, "v_max_u16", VOP_I16_I16_I16>;
 defm V_MAX_I16 : VOP2Inst <vop2<0,0x30>, "v_max_i16", VOP_I16_I16_I16>;
 defm V_MIN_U16 : VOP2Inst <vop2<0,0x31>, "v_min_u16", VOP_I16_I16_I16>;
 defm V_MIN_I16 : VOP2Inst <vop2<0,0x32>, "v_min_i16", VOP_I16_I16_I16>;
 } // End isCommutable = 1
 defm V_LDEXP_F16 : VOP2Inst <vop2<0,0x33>, "v_ldexp_f16", VOP_F16_F16_I16>;
 
+//===----------------------------------------------------------------------===//
+// VOP3 Instructions
+//===----------------------------------------------------------------------===//
+let isCommutable = 1 in {
+    defm V_MAD_F16 : VOP3Inst <vop3<0, 0x1ea>, "v_mad_f16", VOP_F16_F16_F16_F16>;
+    defm V_MAD_U16 : VOP3Inst <vop3<0, 0x1eb>, "v_mad_u16", VOP_I16_I16_I16_I16>;
+    defm V_MAD_I16 : VOP3Inst <vop3<0, 0x1ec>, "v_mad_i16", VOP_I16_I16_I16_I16>;
+}
 } // let DisableSIDecoder = 1
 
 // Aliases to simplify matching of floating-point instructions that
 // are VOP2 on SI and VOP3 on VI.
 
 class SI2_VI3Alias <string name, Instruction inst> : InstAlias <
   name#" $dst, $src0, $src1",
   (inst VGPR_32:$dst, 0, VCSrc_32:$src0, 0, VCSrc_32:$src1, 0, 0)