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AMDGPU: Run verifier after 2nd run of SIShrinkInstructions
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Authored by arsenm on Jun 10 2016, 4:04 PM.

Reviewers

• tstellarAMD

arsenm retitled this revision from to AMDGPU: Run verifier after 2nd run of SIShrinkInstructions.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

LGTM.

This revision is now accepted and ready to land.Jun 14 2016, 6:05 PM

r273469

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Size

lib/

Target/

AMDGPU/

2 lines

Show First 20 Lines • Show All 378 Lines • ▼ Show 20 Lines	if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
// Don't do this with no optimizations since it throws away debug info by		// Don't do this with no optimizations since it throws away debug info by
// merging nonadjacent loads.		// merging nonadjacent loads.

// This should be run after scheduling, but before register allocation. It		// This should be run after scheduling, but before register allocation. It
// also need extra copies to the address operand to be eliminated.		// also need extra copies to the address operand to be eliminated.
insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);		insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
insertPass(&MachineSchedulerID, &RegisterCoalescerID);		insertPass(&MachineSchedulerID, &RegisterCoalescerID);
}		}
addPass(createSIShrinkInstructionsPass(), false);		addPass(createSIShrinkInstructionsPass());
addPass(createSIWholeQuadModePass());		addPass(createSIWholeQuadModePass());
}		}

void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {		void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
TargetPassConfig::addFastRegAlloc(RegAllocPass);		TargetPassConfig::addFastRegAlloc(RegAllocPass);
}		}

void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {		void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
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