AMDGPU/SI: Correctly encode constant expressions

[• tstellarAMD]

Summary

We we have an MCConstantExpr, we can encode it directly into the instruction
instead of emitting fixups.

[artem.tamazov]

LGTM

[artem.tamazov]

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

168

BTW, is it possible to use MCExpr::evaluateAsAbsolute() to to get a "constant" (i.e. known during assembly time) value?

[• tstellarAMD]

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

168

Maybe, I will look into this and do a follow on patch.

[• tstellarAMD]

r272750

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

static uint32_t getLit64Encoding(uint64_t Val) {
   if (Val == DoubleToBits(-4.0))
     return 247;
 
   return 255;
 }
 
 uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
                                          unsigned OpSize) const {
-  if (MO.isExpr())
+
+  int64_t Imm;
+  if (MO.isExpr()) {
+    const MCConstantExpr *C = dyn_cast<MCConstantExpr>(MO.getExpr());
+    if (!C)
       return 255;
 
+    Imm = C->getValue();
+  } else {
+
     assert(!MO.isFPImm());
 
     if (!MO.isImm())
       return ~0;
 
+    Imm = MO.getImm();
+  }
+
   if (OpSize == 4)
-    return getLit32Encoding(static_cast<uint32_t>(MO.getImm()));
+    return getLit32Encoding(static_cast<uint32_t>(Imm));
 
   assert(OpSize == 8);
 
-  return getLit64Encoding(static_cast<uint64_t>(MO.getImm()));
+  return getLit64Encoding(static_cast<uint64_t>(Imm));
 }
 
 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
 
   uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
     if (getLitEncoding(Op, RC.getSize()) != 255)
       continue;
 
     // Yes! Encode it
     int64_t Imm = 0;
 
     if (Op.isImm())
       Imm = Op.getImm();
-    else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
+    else if (Op.isExpr()) {
+      if (const MCConstantExpr *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
+        Imm = C->getValue();
+
+    } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
       llvm_unreachable("Must be immediate or expr");
 
     for (unsigned j = 0; j < 4; j++) {
       OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff));
     }
 
     // Only one literal value allowed
     break;

 
 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
                                             const MCOperand &MO,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
   if (MO.isReg())
     return MRI.getEncodingValue(MO.getReg());
 
-  if (MO.isExpr()) {
+  if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
     const MCSymbolRefExpr *Expr = dyn_cast<MCSymbolRefExpr>(MO.getExpr());
     MCFixupKind Kind;
     if (Expr && Expr->getSymbol().isExternal())
       Kind = FK_Data_4;
     else
       Kind = FK_PCRel_4;
     Fixups.push_back(MCFixup::create(4, MO.getExpr(), Kind, MI.getLoc()));
   }

test/MC/AMDGPU/expressions.s

 // VI-NEXT: ;   fixup A - offset: 4, value: gds+4, kind: FK_PCRel_4
 
 // Consecutive instructions with no blank line in between to make sure we
 // don't call Lex() too many times.
 s_add_u32 s0, s0, global+4
 s_addc_u32 s1, s1, 0
 // VI: s_add_u32 s0, s0, global+4
 // VI: s_addc_u32 s1, s1, 0
+
+// Use a computed expression that results in an inline immediate.
+.set foo, 4
+s_mov_b32 s0, foo+2
+// VI: s_mov_b32 s0, 6 ; encoding: [0x86,0x00,0x80,0xbe]
+
+// Use a computed expression that results in a non-inline immediate.
+.set foo, 512
+s_mov_b32 s0, foo+2
+// VI: s_mov_b32 s0, 514 ; encoding: [0xff,0x00,0x80,0xbe,0x02,0x02,0x00,0x00]