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AMDGPU: Temporary fix for broken store combine
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Authored by arsenm on May 25 2016, 12:23 PM.

Reviewers

• tstellarAMD
nhaehnle

arsenm retitled this revision from to AMDGPU: Temporary fix for broken store combine.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

ping

LGTM

This revision is now accepted and ready to land.Jun 1 2016, 6:30 AM

r271567

Path

Size

lib/

Target/

AMDGPU/

2 lines

test/

CodeGen/

AMDGPU/

13 lines

Show First 20 Lines • Show All 2,186 Lines • ▼ Show 20 Lines	if (isTypeLegal(VT) \|\| SN->isVolatile() \|\|
!ISD::isNormalLoad(Value.getNode()) \|\| VT.getSizeInBits() < 8)		!ISD::isNormalLoad(Value.getNode()) \|\| VT.getSizeInBits() < 8)
return SDValue();		return SDValue();

LoadSDNode *LoadVal = cast<LoadSDNode>(Value);		LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
if (LoadVal->isVolatile() \|\| !usesAllNormalStores(LoadVal))		if (LoadVal->isVolatile() \|\| !usesAllNormalStores(LoadVal))
return SDValue();		return SDValue();

EVT MemVT = LoadVal->getMemoryVT();		EVT MemVT = LoadVal->getMemoryVT();
		if (!MemVT.isRound())
		return SDValue();

SDLoc SL(N);		SDLoc SL(N);
SelectionDAG &DAG = DCI.DAG;		SelectionDAG &DAG = DCI.DAG;
EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);		EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);

SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,		SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
LoadVT, SL,		LoadVT, SL,
LoadVal->getChain(),		LoadVal->getChain(),
▲ Show 20 Lines • Show All 709 Lines • Show Last 20 Lines

	Show First 20 Lines • Show All 175 Lines • ▼ Show 20 Lines
	define void @load_v2i16_sext(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) {			define void @load_v2i16_sext(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) {
	entry:			entry:
	%0 = load <2 x i16>, <2 x i16> addrspace(1)* %in			%0 = load <2 x i16>, <2 x i16> addrspace(1)* %in
	%1 = sext <2 x i16> %0 to <2 x i32>			%1 = sext <2 x i16> %0 to <2 x i32>
	store <2 x i32> %1, <2 x i32> addrspace(1)* %out			store <2 x i32> %1, <2 x i32> addrspace(1)* %out
	ret void			ret void
	}			}

				; FUNC-LABEL: {{^}}global_load_v3i16:
				; SI-NOHSA: buffer_load_dwordx2 v
				; SI-HSA: flat_load_dwordx2 v

				; R600-DAG: VTX_READ_32
				; R600-DAG: VTX_READ_16
				define void @global_load_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %in) {
				entry:
				%ld = load <3 x i16>, <3 x i16> addrspace(1)* %in
				store <3 x i16> %ld, <3 x i16> addrspace(1)* %out
				ret void
				}

	; FUNC-LABEL: {{^}}load_v4i16:			; FUNC-LABEL: {{^}}load_v4i16:
	; R600: VTX_READ_16			; R600: VTX_READ_16
	; R600: VTX_READ_16			; R600: VTX_READ_16
	; R600: VTX_READ_16			; R600: VTX_READ_16
	; R600: VTX_READ_16			; R600: VTX_READ_16
	; SI-NOHSA: buffer_load_ushort			; SI-NOHSA: buffer_load_ushort
	; SI-NOHSA: buffer_load_ushort			; SI-NOHSA: buffer_load_ushort
	; SI-NOHSA: buffer_load_ushort			; SI-NOHSA: buffer_load_ushort
	▲ Show 20 Lines • Show All 546 Lines • Show Last 20 Lines