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Differential D20489

AMDGPU: Fix relationship between SReg_32 and SReg_32_XM0
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Authored by arsenm on May 20 2016, 1:50 PM.

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• tstellarAMD

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arsenm updated this revision to Diff 57985.May 20 2016, 1:50 PM
arsenm retitled this revision from to AMDGPU: Fix relationship between SReg_32 and SReg_32_XM0.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added subscribers: kzhuravl, arsenm. · View Herald TranscriptMay 20 2016, 1:50 PM
• tstellarAMD accepted this revision.May 20 2016, 5:23 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.May 20 2016, 5:23 PM
arsenm closed this revision.May 20 2016, 6:00 PM

r270300

Revision Contents

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lib/
Target/
AMDGPU/
11 lines

Diff 57985

lib/Target/AMDGPU/SIRegisterInfo.td

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// Register classes used as source and destination // Register classes used as source and destination
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class RegImmMatcher<string name> : AsmOperandClass { class RegImmMatcher<string name> : AsmOperandClass {
let Name = name; let Name = name;
let RenderMethod = "addRegOrImmOperands"; let RenderMethod = "addRegOrImmOperands";
} }
// Register class for all scalar registers (SGPRs + Special Registers)
def SReg_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
(add SGPR_32, M0, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)
>;
// Subset of SReg_32 without M0 for SMRD instructions and alike. // Subset of SReg_32 without M0 for SMRD instructions and alike.
// See comments in SIInstructions.td for more info. // See comments in SIInstructions.td for more info.
def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32], 32, def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32], 32,
(add SGPR_32, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI, (add SGPR_32, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI) TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)
>; >;
// Register class for all scalar registers (SGPRs + Special Registers)
def SReg_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
(add SReg_32_XM0, M0)
>;
def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)>; def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)>;
def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)> { def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32, def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
(add SGPR_64, VCC, EXEC, FLAT_SCR, TTMP_64, TBA, TMA) (add SGPR_64, VCC, EXEC, FLAT_SCR, TTMP_64, TBA, TMA)
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