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Differential D20265

AMDGPU: Fix verifier error when spilling undef subreg
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Authored by arsenm on May 13 2016, 5:08 PM.

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• tstellarAMD

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arsenm updated this revision to Diff 57271.May 13 2016, 5:08 PM

arsenm retitled this revision from to AMDGPU: Fix verifier error when spilling undef subreg.

arsenm updated this object.

arsenm added a reviewer: • tstellarAMD.

arsenm added a subscriber: llvm-commits.

Herald added subscribers: kzhuravl, arsenm. · View Herald TranscriptMay 13 2016, 5:08 PM

LGTM.

This revision is now accepted and ready to land.May 18 2016, 10:34 AM

r270002

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lib/

Target/

AMDGPU/

SIRegisterInfo.cpp

14 lines

Diff 57271

lib/Target/AMDGPU/SIRegisterInfo.cpp

Show First 20 Lines • Show All 499 Lines • ▼ Show 20 Lines	switch (MI->getOpcode()) {
case AMDGPU::SI_SPILL_S512_SAVE:		case AMDGPU::SI_SPILL_S512_SAVE:
case AMDGPU::SI_SPILL_S256_SAVE:		case AMDGPU::SI_SPILL_S256_SAVE:
case AMDGPU::SI_SPILL_S128_SAVE:		case AMDGPU::SI_SPILL_S128_SAVE:
case AMDGPU::SI_SPILL_S64_SAVE:		case AMDGPU::SI_SPILL_S64_SAVE:
case AMDGPU::SI_SPILL_S32_SAVE: {		case AMDGPU::SI_SPILL_S32_SAVE: {
unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());		unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);		unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);

		unsigned SuperReg = MI->getOperand(0).getReg();
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {		for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),		unsigned SubReg = getPhysRegSubReg(SuperReg,
&AMDGPU::SGPR_32RegClass, i);		&AMDGPU::SGPR_32RegClass, i);

struct SIMachineFunctionInfo::SpilledReg Spill =		struct SIMachineFunctionInfo::SpilledReg Spill =
MFI->getSpilledReg(MF, Index, i);		MFI->getSpilledReg(MF, Index, i);

if (Spill.hasReg()) {		if (Spill.hasReg()) {
BuildMI(*MBB, MI, DL,		BuildMI(*MBB, MI, DL,
TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),		TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
Spill.VGPR)		Spill.VGPR)
.addReg(SubReg)		.addReg(SubReg)
.addImm(Spill.Lane);		.addImm(Spill.Lane);

// FIXME: Since this spills to another register instead of an actual		// FIXME: Since this spills to another register instead of an actual
// frame index, we should delete the frame index when all references to		// frame index, we should delete the frame index when all references to
// it are fixed.		// it are fixed.
} else {		} else {
// Spill SGPR to a frame index.		// Spill SGPR to a frame index.
// FIXME we should use S_STORE_DWORD here for VI.		// FIXME we should use S_STORE_DWORD here for VI.
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)		MachineInstrBuilder Mov
		= BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
.addReg(SubReg);		.addReg(SubReg);

		// There could be undef components of a spilled super register.
		// TODO: Can we detect this and skip the spill?
		if (NumSubRegs > 1)
		Mov.addReg(SuperReg, RegState::Implicit);

unsigned Size = FrameInfo->getObjectSize(Index);		unsigned Size = FrameInfo->getObjectSize(Index);
unsigned Align = FrameInfo->getObjectAlignment(Index);		unsigned Align = FrameInfo->getObjectAlignment(Index);
MachinePointerInfo PtrInfo		MachinePointerInfo PtrInfo
= MachinePointerInfo::getFixedStack(*MF, Index);		= MachinePointerInfo::getFixedStack(*MF, Index);
MachineMemOperand *MMO		MachineMemOperand *MMO
= MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,		= MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
Size, Align);		Size, Align);
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE))		BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE))
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