AMDGPU: Remove verifier check for scc live ins

[arsenm]

Summary

We only really need this to be true for SIFixSGPRCopies.
I'm not sure there's any way this could happen before that point.

Fixes a case where MachineCSE could introduce a cross block
scc use.

[arsenm]

Attach right patch

[• tstellarAMD]

LGTM.

[arsenm]

r269391

lib/Target/AMDGPU/SIInstrInfo.cpp

 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
                                     StringRef &ErrInfo) const {
   uint16_t Opcode = MI->getOpcode();
   const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
   int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
   int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
   int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
 
-  // Make sure we don't have SCC live-ins to basic blocks.  moveToVALU assumes
-  // all SCC users are in the same blocks as their defs.
-  const MachineBasicBlock *MBB = MI->getParent();
-  if (MI == &MBB->front()) {
-    if (MBB->isLiveIn(AMDGPU::SCC)) {
-      ErrInfo = "scc register cannot be live across blocks.";
-      return false;
-    }
-  }
-
   // Make sure the number of operands is correct.
   const MCInstrDesc &Desc = get(Opcode);
   if (!Desc.isVariadic() &&
       Desc.getNumOperands() != MI->getNumExplicitOperands()) {
      ErrInfo = "Instruction has wrong number of operands.";
      return false;
   }
 

test/CodeGen/AMDGPU/uniform-cfg.ll

 ; SI: v_cmp_lt_i32_e64 [[MASK:s\[[0-9]+:[0-9]+\]]], 0, [[COND]]
 ; SI: s_and_b64 vcc, exec, [[MASK]]
 ; SI: s_cbranch_vccnz [[EXIT]]
 ; SI: buffer_store
 ; SI: {{^}}[[EXIT]]:
 ; SI: s_endpgm
 define void @icmp_users_different_blocks(i32 %cond, i32 addrspace(1)* %out) {
 bb:
-  %tmp = tail call i32 @llvm.r600.read.tidig.x() #0
+  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
   %tmp1 = icmp sgt i32 %cond, 0
   br i1 %tmp1, label %bb2, label %bb9
 
 bb2:                                              ; preds = %bb
   %tmp2 = sext i1 %tmp1 to i32
   %tmp3 = add i32 %tmp2, %tmp
   br i1 %tmp1, label %bb9, label %bb7
 

 ; SI: s_xor_b64  [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
 ; SI: s_cbranch_execz [[ENDIF_LABEL:[0-9_A-Za-z]+]]
 ; SI: s_cmp_lg_i32 {{s[0-9]+}}, 0
 ; SI: s_cbranch_scc1 [[ENDIF_LABEL]]
 ; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
 ; SI: buffer_store_dword [[ONE]]
 define void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) {
 entry:
-  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
   %d_cmp = icmp ult i32 %tid, 16
   br i1 %d_cmp, label %if, label %endif
 
 if:
   store i32 0, i32 addrspace(1)* %out
   %u_cmp = icmp eq i32 %cond, 0
   br i1 %u_cmp, label %if_uniform, label %endif
 

 ; SI: s_endpgm
 define void @divergent_inside_uniform(i32 addrspace(1)* %out, i32 %cond) {
 entry:
   %u_cmp = icmp eq i32 %cond, 0
   br i1 %u_cmp, label %if, label %endif
 
 if:
   store i32 0, i32 addrspace(1)* %out
-  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
   %d_cmp = icmp ult i32 %tid, 16
   br i1 %d_cmp, label %if_uniform, label %endif
 
 if_uniform:
   store i32 1, i32 addrspace(1)* %out
   br label %endif
 
 endif:
   ret void
 }
 
-; SI: {{^}}divergent_if_uniform_if:
+; SI-LABEL: {{^}}divergent_if_uniform_if:
 ; SI: v_cmp_eq_i32_e32 vcc, 0, v0
 ; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
 ; SI: s_xor_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
 ; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
 ; SI: buffer_store_dword [[ONE]]
 ; SI: s_or_b64 exec, exec, [[MASK]]
 ; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0
 ; SI: s_cbranch_scc1 [[EXIT:[A-Z0-9_]+]]
 ; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
 ; SI: buffer_store_dword [[TWO]]
 ; SI: [[EXIT]]:
 ; SI: s_endpgm
 define void @divergent_if_uniform_if(i32 addrspace(1)* %out, i32 %cond) {
 entry:
-  %tid = call i32 @llvm.r600.read.tidig.x() #0
+  %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
   %d_cmp = icmp eq i32 %tid, 0
   br i1 %d_cmp, label %if, label %endif
 
 if:
   store i32 1, i32 addrspace(1)* %out
   br label %endif
 
 endif:
   %u_cmp = icmp eq i32 %cond, 0
   br i1 %u_cmp, label %if_uniform, label %exit
 
 if_uniform:
   store i32 2, i32 addrspace(1)* %out
   br label %exit
 
 exit:
   ret void
 }
 
-declare i32 @llvm.r600.read.tidig.x() #0
+; The condition of the branches in the two blocks are
+; uniform. MachineCSE replaces the 2nd condition with the inverse of
+; the first, leaving an scc use in a different block than it was
+; defed.
+
+; SI-LABEL: {{^}}cse_uniform_condition_different_blocks:
+; SI: s_load_dword [[COND:s[0-9]+]]
+; SI: s_cmp_lt_i32 [[COND]], 1
+; SI: s_cbranch_scc1 BB13_3
+
+; SI: BB#1:
+; SI-NOT: cmp
+; SI: buffer_load_dword
+; SI: buffer_store_dword
+; SI: s_cbranch_scc1 BB13_3
+
+; SI: BB13_3:
+; SI: s_endpgm
+define void @cse_uniform_condition_different_blocks(i32 %cond, i32 addrspace(1)* %out) {
+bb:
+  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
+  %tmp1 = icmp sgt i32 %cond, 0
+  br i1 %tmp1, label %bb2, label %bb9
+
+bb2:                                              ; preds = %bb
+  %tmp3 = load volatile i32, i32 addrspace(1)* undef
+  store volatile i32 0, i32 addrspace(1)* undef
+  %tmp9 = icmp sle i32 %cond, 0
+  br i1 %tmp9, label %bb9, label %bb7
+
+bb7:                                              ; preds = %bb5
+  store i32 %tmp3, i32 addrspace(1)* %out
+  br label %bb9
+
+bb9:                                              ; preds = %bb8, %bb4
+  ret void
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 attributes #0 = { readnone }