AMDGPU: Uniform branch conditions can originate with intrinsics

[nhaehnle]

Summary

Discovered by Dave Airlie, fixes an assertion in Khronos OpenGL CTS
GL43-CTS.shader_storage_buffer_object.advanced-matrix.

In this particular case, the buffer load intrinsic fed into a uniform
conditional branch, and led the brcond lowering down the wrong path.

[arsenm]

LGTM

test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll

4–5 ↗

(On Diff #56189)

This can be removed

7 ↗

(On Diff #56189)

Space after ;

llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

if (Intr->getOpcode() == ISD::SETCC) {
     Intr = SetCC->getOperand(0).getNode();
 
   } else {
     // Get the target from BR if we don't negate the condition
     BR = findUser(BRCOND, ISD::BR);
     Target = BR->getOperand(1);
   }
 
-  if (Intr->getOpcode() != ISD::INTRINSIC_W_CHAIN) {
+  if (!isCFIntrinsic(Intr)) {
     // This is a uniform branch so we don't need to legalize.
     return BRCOND;
   }
 
   assert(!SetCC ||
         (SetCC->getConstantOperandVal(1) == 1 &&
-         isCFIntrinsic(Intr) &&
          cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
                                                              ISD::SETNE));
 
   // Build the result and
   ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
 
   // operands of the new intrinsic call
   SmallVector<SDValue, 4> Ops;

llvm/trunk/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll

+; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
+
+; This used to raise an assertion due to how the choice between uniform and
+; non-uniform branches was determined.
+;
+; CHECK-LABEL: {{^}}main:
+; CHECK: s_cbranch_vccnz
+define amdgpu_ps float @main(<4 x i32> inreg %rsrc) {
+main_body:
+  %v = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 true, i1 false)
+  %cc = fcmp une float %v, 1.000000e+00
+  br i1 %cc, label %if, label %else
+
+if:
+  %u = fadd float %v, %v
+  br label %else
+
+else:
+  %r = phi float [ %v, %main_body ], [ %u, %if ]
+  ret float %r
+}
+
+; Function Attrs: nounwind readonly
+declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0
+
+attributes #0 = { nounwind readonly }