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Differential D19745

AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratch
ClosedPublic

Authored by • tstellarAMD on Apr 29 2016, 2:05 PM.

Details

Reviewers
arsenm
Commits
rGbd5e44312c33: Merging r268295:
rG154c9cdd2418: AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratch
rL268295: AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratch
Summary

We were using v_readlane_b32 with the lane set to zero, but this won't
work if thread 0 is not active.

Diff Detail

Repository
rL LLVM

Event Timeline

• tstellarAMD updated this revision to Diff 55665.Apr 29 2016, 2:05 PM
• tstellarAMD retitled this revision from to AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratch.
• tstellarAMD updated this object.
• tstellarAMD added a reviewer: arsenm.
• tstellarAMD added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptApr 29 2016, 2:05 PM
arsenm accepted this revision.Apr 29 2016, 2:12 PM
arsenm edited edge metadata.

LGTM

This revision is now accepted and ready to land.Apr 29 2016, 2:12 PM
Closed by commit rL268295: AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratch (authored by tstellar). · Explain WhyMay 2 2016, 1:17 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
3 lines
test/
CodeGen/
AMDGPU/
2 lines

Diff 55881

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp

Show First 20 Lines • Show All 583 Lines • ▼ Show 20 Lines case AMDGPU::SI_SPILL_S32_RESTORE: {
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg) BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg)
.addFrameIndex(Index) // frame_idx .addFrameIndex(Index) // frame_idx
.addReg(MFI->getScratchRSrcReg()) // scratch_rsrc .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
.addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
.addImm(i * 4) // offset .addImm(i * 4) // offset
.addMemOperand(MMO); .addMemOperand(MMO);
BuildMI(*MBB, MI, DL, BuildMI(*MBB, MI, DL,
TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), SubReg) TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)
.addReg(TmpReg, RegState::Kill) .addReg(TmpReg, RegState::Kill)
.addImm(0)
.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
} }
} }
MI->eraseFromParent(); MI->eraseFromParent();
break; break;
} }
▲ Show 20 Lines • Show All 386 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll

; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck %s
; Make sure this doesn't crash. ; Make sure this doesn't crash.
; CHECK: {{^}}test: ; CHECK: {{^}}test:
; Make sure we are handling hazards correctly. ; Make sure we are handling hazards correctly.
; CHECK: buffer_load_dword [[VHI:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:12 ; CHECK: buffer_load_dword [[VHI:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:12
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_readlane_b32 s[[HI:[0-9]+]], [[VHI]] ; CHECK-NEXT: v_readfirstlane_b32 s[[HI:[0-9]+]], [[VHI]]
; CHECK-NEXT: s_nop 4 ; CHECK-NEXT: s_nop 4
; CHECK-NEXT: buffer_store_dword v0, off, s[0:[[HI]]{{\]}}, 0 ; CHECK-NEXT: buffer_store_dword v0, off, s[0:[[HI]]{{\]}}, 0
; CHECK: s_endpgm ; CHECK: s_endpgm
define void @test(i32 addrspace(1)* %out, i32 %in) { define void @test(i32 addrspace(1)* %out, i32 %in) {
call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" () call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" ()
call void asm sideeffect "", "~{SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15}" () call void asm sideeffect "", "~{SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15}" ()
call void asm sideeffect "", "~{SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23}" () call void asm sideeffect "", "~{SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23}" ()
call void asm sideeffect "", "~{SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31}" () call void asm sideeffect "", "~{SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31}" ()
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines