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[mips][atomics] Fix atomic instruction descriptions and uses.
ClosedPublic

Authored by sdardis on Apr 29 2016, 5:03 AM.

Details

Summary

PR/27458 highlights that the MIPS backend does not have well formed
MIR for atomic operations (among other errors).

This patch adds expands and corrects the LL/SC descriptions and uses
for MIPS(64).

Diff Detail

Event Timeline

sdardis updated this revision to Diff 55574.Apr 29 2016, 5:03 AM
sdardis retitled this revision from to [mips][atomics] Fix atomic instruction descriptions and uses..
sdardis updated this object.
sdardis added a reviewer: dsanders.
sdardis set the repository for this revision to rL LLVM.
sdardis added a subscriber: llvm-commits.
dsanders requested changes to this revision.Apr 29 2016, 9:41 AM
dsanders edited edge metadata.
dsanders added inline comments.
lib/Target/Mips/Mips32r6InstrInfo.td
654

I think this and the other mayLoad/mayStores are redundant. According to tablegen's comments, both mayLoad and mayStore default to false (unless the pattern contains a load or store).

lib/Target/Mips/Mips64InstrInfo.td
205

Am I right in thinking that these are marked codegen-only because the disassembler complains about an encoding conflict?

If so, we should handle this with predicates (similar to GPR_32/GPR_64 but for pointer size) so that the assembler/disassembler pick the right version.

test/CodeGen/Mips/atomic.ll
1

This looks like a formatting-only change to me. Am I missing something?

This revision now requires changes to proceed.Apr 29 2016, 9:41 AM
sdardis added inline comments.Apr 29 2016, 10:44 AM
test/CodeGen/Mips/atomic.ll
1

I reformatted the lines and added -verify-machineinstrs to cover the mips32r2, mips32r6, mips64r2 and mips64r6. There didn't seem to be any need to cover all of the cases that would be applicable. That could be added if requested.

sdardis updated this revision to Diff 56890.May 11 2016, 6:04 AM
sdardis edited edge metadata.

Addressed reviewers comments.

dsanders accepted this revision.May 17 2016, 3:15 AM
dsanders edited edge metadata.

LGTM

lib/Target/Mips/MipsInstrInfo.td
182

Indentation. Likewise for the next def

This revision is now accepted and ready to land.May 17 2016, 3:15 AM
sdardis updated this revision to Diff 57480.May 17 2016, 8:00 AM
sdardis edited edge metadata.
sdardis removed rL LLVM as the repository for this revision.

Addressed comments. Precommit testing caught using PTR_32/PTR_64 were InsnPredicates which clobber the ISA_MIPS* family of predicates. I've changed it to GPRPredicates, that ok?

Addressed comments. Precommit testing caught using PTR_32/PTR_64 were InsnPredicates which clobber the ISA_MIPS* family of predicates. I've changed it to GPRPredicates, that ok?

It will need to be a new sub-list. Putting it in GPRPredicates will clobber GPR_32/GPR_64.

sdardis updated this revision to Diff 59717.Jun 6 2016, 6:55 AM

Remove PTR_32 / PTR_64 and used IsPTR32bit / IsPTR64bit like we use InMicroMipsMode rather than having AdditionalPredicates and YetMorePredicates.

Thanks,
Simon

dsanders requested changes to this revision.Jun 6 2016, 7:40 AM
dsanders edited edge metadata.

Remove PTR_32 / PTR_64 and used IsPTR32bit / IsPTR64bit like we use InMicroMipsMode rather than having AdditionalPredicates and YetMorePredicates.

Thanks,
Simon

AdditionalPredicates is just for predicates we haven't got around to sorting out yet so we shouldn't add new predicates to it. We should also be removing any uses of Predicates or AdditionalPredicates where they remain.

The intent of the PredicateControl class was to have a sub-list for each mutually exclusive group of predicates with the final Predicates field being the concatenation of all the sub-lists. This allowed us to override specific groups of predicates which fixed a recurring problem where careless use of a 'let Predicates = ...' statement would accidentally remove predicates from an instruction. If we've got a new mutually exclusive group then we should add a new sub-list to PredicateControl.

This revision now requires changes to proceed.Jun 6 2016, 7:40 AM
sdardis updated this revision to Diff 60149.Jun 9 2016, 2:46 AM
sdardis edited edge metadata.

Added a new sublist to predicate control.

dsanders accepted this revision.Jun 13 2016, 3:00 AM
dsanders edited edge metadata.

LGTM with PTRPredicates in the listconcat and a couple nits.

lib/Target/Mips/Mips.td
37–42 ↗(On Diff #60149)

You need to add PTRPredicates to this listconcat() for the predicates in the sublist to take effect.

Once you've fixed this, we shouldn't need the separate DecoderNamespace anymore but tablegen might not be able to figure this out (it couldn't for the GPR_64 case). If we can eliminate the separate namespace then please do so, but I'm ok with it if we can't.

lib/Target/Mips/Mips32r6InstrInfo.td
762

Could you move this one back down to the SDBBP instruction? The instructions in this file are in alphabetical order

lib/Target/Mips/MipsInstrInfo.td
182

This indentation hasn't been corrected

This revision is now accepted and ready to land.Jun 13 2016, 3:00 AM
sdardis closed this revision.Jun 14 2016, 5:23 AM

Thanks, committed as rL272655. I wasn't able to eliminate the decoder namespace.

I wasn't able to eliminate the decoder namespace.

Thanks for trying. Hopefully we'll figure out why tablegen can't see that an instruction with FeaturePTR64Bit can't conflict with an instruction with !FeaturePTR64Bit.