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Differential D19316

[ppc64] Reenable sibling call optimization on ppc64 since fixed tsan library tail-call issue
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Authored by cycheng on Apr 20 2016, 4:07 AM.

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Reviewers

kbarton
nemanjai

Summary

print-stack-trace.cc test failure of compiler-rt has been fixed by r266869 (http://reviews.llvm.org/D19148), so reenable sibling call optimization on ppc64

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Event Timeline

cycheng updated this revision to Diff 54340.Apr 20 2016, 4:07 AM

cycheng retitled this revision from to [ppc64] Reenable sibling call optimization on ppc64 since fixed tsan library tail-call issue.

cycheng updated this object.

cycheng added reviewers: kbarton, nemanjai.

cycheng added subscribers: hfinkel, tjablin, llvm-commits.

LGTM

This revision is now accepted and ready to land.Apr 25 2016, 12:31 PM

Committed r267527

Revision Contents

Path

Size

docs/

ReleaseNotes.rst

1 line

lib/

Target/

PowerPC/

PPCISelLowering.cpp

2 lines

Diff 54340

docs/ReleaseNotes.rst

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	During this release ...			During this release ...


	Changes to the PowerPC Target			Changes to the PowerPC Target
	-----------------------------			-----------------------------

	Moved some optimizations from O3 to O2 (D18562)			Moved some optimizations from O3 to O2 (D18562)

				* Enable sibling call optimization on ppc64 ELFv1/ELFv2 abi

	Changes to the X86 Target			Changes to the X86 Target
	-------------------------			-------------------------

	* LLVM now supports the Intel CPU codenamed Skylake Server with AVX-512			* LLVM now supports the Intel CPU codenamed Skylake Server with AVX-512
	extensions using ``-march=skylake-avx512``. The switch enables the			extensions using ``-march=skylake-avx512``. The switch enables the
	ISA extensions AVX-512{F, CD, VL, BW, DQ}.			ISA extensions AVX-512{F, CD, VL, BW, DQ}.

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lib/Target/PowerPC/PPCISelLowering.cpp

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	cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);			cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);

	static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",			static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
	cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);			cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);

	static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",			static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
	cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);			cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);

	static cl::opt<bool> DisableSCO("disable-ppc-sco", cl::init(true),			static cl::opt<bool> DisableSCO("disable-ppc-sco",
	cl::desc("disable sibling call optimization on ppc"), cl::Hidden);			cl::desc("disable sibling call optimization on ppc"), cl::Hidden);

	STATISTIC(NumTailCalls, "Number of tail calls");			STATISTIC(NumTailCalls, "Number of tail calls");
	STATISTIC(NumSiblingCalls, "Number of sibling calls");			STATISTIC(NumSiblingCalls, "Number of sibling calls");

	// FIXME: Remove this once the bug has been fixed!			// FIXME: Remove this once the bug has been fixed!
	extern cl::opt<bool> ANDIGlueBug;			extern cl::opt<bool> ANDIGlueBug;

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