Disable quad load/store pairing for Exynos

[az]

Summary

Disable load/store pairing for quads on -mcpu=exynos-m1 as it is not as efficient as the non paired ld/st.

[mcrosier]

LGTM.

[mcrosier]

You might want to also add a test that shows these type of loads are not clustered by the MI scheduler. You should add the test to test/CodeGen/AArch64/arm64-ldp-cluster.ll

[az]

Added no load clustering test for Exynos.

[junbuml]

llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll

132

Since you only disable clustering for quad load/store, you may want to add check for EXYNOS in above other test cases.

[mcrosier]

llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll

132

I tend to agree.

[az]

Added check for EXYNOS in the other test cases (made also the new Exynos test case do the CHECK but can undo it if not seen useful)

[evandro]

LGTM

[mcrosier]

LGTM. Feel free to commit.

[sebpop]

Committed to LLVM trunk as r266223.

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

bool AArch64InstrInfo::isCandidateToMergeOrPair(MachineInstr *MI) const {
   if (MI->modifiesRegister(BaseReg, TRI))
     return false;
 
   // Check if this load/store has a hint to avoid pair formation.
   // MachineMemOperands hints are set by the AArch64StorePairSuppress pass.
   if (isLdStPairSuppressed(MI))
     return false;
 
+  // Do not pair quad ld/st for Exynos.
+  if (Subtarget.isExynosM1()) {
+      switch (MI->getOpcode()) {
+        default:
+          break;
+
+        case AArch64::LDURQi:
+        case AArch64::STURQi:
+        case AArch64::LDRQui:
+        case AArch64::STRQui:
+          return false;
+        }
+    }
+
   return true;
 }
 
 bool AArch64InstrInfo::getMemOpBaseRegImmOfs(
     MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset,
     const TargetRegisterInfo *TRI) const {
   switch (LdSt->getOpcode()) {
   default:

llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOS %s
 
 ; Test ldr clustering.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldr_int:BB#0
 ; CHECK: Cluster loads SU(1) - SU(2)
 ; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
 ; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; EXYNOS: ********** MI Scheduling **********
+; EXYNOS-LABEL: ldr_int:BB#0
+; EXYNOS: Cluster loads SU(1) - SU(2)
+; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
 define i32 @ldr_int(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 1
   %tmp1 = load i32, i32* %p1, align 2
   %p2 = getelementptr inbounds i32, i32* %a, i32 2
   %tmp2 = load i32, i32* %p2, align 2
   %tmp3 = add i32 %tmp1, %tmp2
   ret i32 %tmp3
 }
 
 ; Test ldpsw clustering
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldp_sext_int:BB#0
 ; CHECK: Cluster loads SU(1) - SU(2)
 ; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRSWui
 ; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: ********** MI Scheduling **********
+; EXYNOS-LABEL: ldp_sext_int:BB#0
+; EXYNOS: Cluster loads SU(1) - SU(2)
+; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRSWui
 define i64 @ldp_sext_int(i32* %p) nounwind {
   %tmp = load i32, i32* %p, align 4
   %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
   %tmp1 = load i32, i32* %add.ptr, align 4
   %sexttmp = sext i32 %tmp to i64
   %sexttmp1 = sext i32 %tmp1 to i64
   %add = add nsw i64 %sexttmp1, %sexttmp
   ret i64 %add
 }
 
 ; Test ldur clustering.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldur_int:BB#0
 ; CHECK: Cluster loads SU(2) - SU(1)
 ; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDURWi
 ; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDURWi
+; EXYNOS: ********** MI Scheduling **********
+; EXYNOS-LABEL: ldur_int:BB#0
+; EXYNOS: Cluster loads SU(2) - SU(1)
+; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDURWi
+; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDURWi
 define i32 @ldur_int(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 -1
   %tmp1 = load i32, i32* %p1, align 2
   %p2 = getelementptr inbounds i32, i32* %a, i32 -2
   %tmp2 = load i32, i32* %p2, align 2
   %tmp3 = add i32 %tmp1, %tmp2
   ret i32 %tmp3
 }
 
 ; Test sext + zext clustering.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldp_half_sext_zext_int:BB#0
 ; CHECK: Cluster loads SU(3) - SU(4)
 ; CHECK: SU(3):   %vreg{{[0-9]+}}<def> = LDRSWui
 ; CHECK: SU(4):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; EXYNOS: ********** MI Scheduling **********
+; EXYNOS-LABEL: ldp_half_sext_zext_int:BB#0
+; EXYNOS: Cluster loads SU(3) - SU(4)
+; EXYNOS: SU(3):   %vreg{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(4):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
 define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
   %tmp0 = load i64, i64* %q, align 4
   %tmp = load i32, i32* %p, align 4
   %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
   %tmp1 = load i32, i32* %add.ptr, align 4
   %sexttmp = sext i32 %tmp to i64
   %sexttmp1 = zext i32 %tmp1 to i64
   %add = add nsw i64 %sexttmp1, %sexttmp
   %add1 = add nsw i64 %add, %tmp0
   ret i64 %add1
 }
 
 ; Test zext + sext clustering.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldp_half_zext_sext_int:BB#0
 ; CHECK: Cluster loads SU(3) - SU(4)
 ; CHECK: SU(3):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
 ; CHECK: SU(4):   %vreg{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: ********** MI Scheduling **********
+; EXYNOS-LABEL: ldp_half_zext_sext_int:BB#0
+; EXYNOS: Cluster loads SU(3) - SU(4)
+; EXYNOS: SU(3):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; EXYNOS: SU(4):   %vreg{{[0-9]+}}<def> = LDRSWui
 define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
   %tmp0 = load i64, i64* %q, align 4
   %tmp = load i32, i32* %p, align 4
   %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
   %tmp1 = load i32, i32* %add.ptr, align 4
   %sexttmp = zext i32 %tmp to i64
   %sexttmp1 = sext i32 %tmp1 to i64
   %add = add nsw i64 %sexttmp1, %sexttmp
   %add1 = add nsw i64 %add, %tmp0
   ret i64 %add1
 }
 
 ; Verify we don't cluster volatile loads.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldr_int_volatile:BB#0
 ; CHECK-NOT: Cluster loads
 ; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
 ; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; EXYNOS: ********** MI Scheduling **********
+; EXYNOS-LABEL: ldr_int_volatile:BB#0
+; EXYNOS-NOT: Cluster loads
+; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
 define i32 @ldr_int_volatile(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 1
   %tmp1 = load volatile i32, i32* %p1, align 2
   %p2 = getelementptr inbounds i32, i32* %a, i32 2
   %tmp2 = load volatile i32, i32* %p2, align 2
   %tmp3 = add i32 %tmp1, %tmp2
   ret i32 %tmp3
 }
+
+; Test ldq clustering (no clustering for Exynos).
+; CHECK: ********** MI Scheduling **********
+; CHECK-LABEL: ldq_cluster:BB#0
+; CHECK: Cluster loads SU(1) - SU(3)
+; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRQui
+; CHECK: SU(3):   %vreg{{[0-9]+}}<def> = LDRQui
+; EXYNOS: ********** MI Scheduling **********
+; EXYNOS-LABEL: ldq_cluster:BB#0
+; EXYNOS-NOT: Cluster loads
+define <2 x i64> @ldq_cluster(i64* %p) {
+  %a1 = bitcast i64* %p to <2 x i64>*
+  %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
+  %add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2
+  %a2 = bitcast i64* %add.ptr2 to <2 x i64>*
+  %tmp2 = add nsw <2 x i64> %tmp1, %tmp1
+  %tmp3 = load <2 x i64>, <2 x i64>* %a2, align 8
+  %res  = mul nsw <2 x i64> %tmp2, %tmp3
+  ret <2 x i64> %res
+}

llvm/test/CodeGen/AArch64/exynos-quad-ldp-stp.ll

+; RUN: llc < %s -march=aarch64 -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s
+
+; CHECK-LABEL: test_exynos_nopair_st
+; CHECK: str
+; CHECK: stur
+; CHECK-NOT: stp
+define void @test_exynos_nopair_st(double* %ptr, <2 x double> %v1, <2 x double> %v2) {
+  %tmp1 = bitcast double* %ptr to <2 x double>*
+  store <2 x double> %v2, <2 x double>* %tmp1, align 16
+  %add.ptr = getelementptr inbounds double, double* %ptr, i64 -2
+  %tmp = bitcast double* %add.ptr to <2 x double>*
+  store <2 x double> %v1, <2 x double>* %tmp, align 16
+  ret void
+}
+
+; CHECK-LABEL: test_exynos_nopair_ld
+; CHECK: ldr
+; CHECK: ldr
+; CHECK-NOT: ldp
+define <2 x i64> @test_exynos_nopair_ld(i64* %p) {
+  %a1 = bitcast i64* %p to <2 x i64>*
+  %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
+  %add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2
+  %a2 = bitcast i64* %add.ptr2 to <2 x i64>*
+  %tmp2 = load <2 x i64>, <2 x i64>* %a2, align 8
+  %add = add nsw <2 x i64> %tmp1, %tmp2
+  ret <2 x i64> %add
+}