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[SystemZ] Add SVC instruction.
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Authored by koriakin on Apr 11 2016, 3:42 AM.

Details

Summary

This is going to be useful for inline assembly only.

Diff Detail

Event Timeline

koriakin retitled this revision from to [SystemZ] Add SVC instruction..
koriakin updated this object.
koriakin added a reviewer: uweigand.
koriakin set the repository for this revision to rL LLVM.
koriakin added a subscriber: llvm-commits.
uweigand edited edge metadata.Apr 11 2016, 4:58 AM

While this is not for CodeGen, I think for the benefit of analysis tools (e.g. LLDB) the pattern should still be marked with the appropriate flags, at least something like "isCall = 1, Defs = [CC]". Not sure if hasSideEffects is necessary, but it probably cannot hurt to add it as well.

Otherweise the patch looks good.

koriakin planned changes to this revision.Apr 11 2016, 5:10 AM
koriakin edited edge metadata.

Added hasSideEffects = 1, Defs = [CC], isCall = 1.

uweigand accepted this revision.Apr 11 2016, 7:39 AM
uweigand edited edge metadata.

LGTM, I'll check it in.

This revision is now accepted and ready to land.Apr 11 2016, 7:39 AM
This revision was automatically updated to reflect the committed changes.