[mips][ias] Correct ELF eflags when Octeon is the target.

[sdardis]

With clang -target mipsel-unknown-linux -mcpu=octeon trival.s -fintegrated-as -c -o blah.o

objdump is giving me:

private flags = 808b0006: [no abi set] [mips64r2] [not32bitmode] [PIC] [CPIC]

The ISA (64r2) and machine type (E_MIPS_MACH_OCTEON) flags seem to be coming out correct, and the EF_MIPS_CPIC / EF_MIPS_PIC are expected.

However GCC / as is giving me:

private flags = 808b0026: [ABI=N32] [mips64r2] [not 32bitmode] [PIC] [CPIC]

The Is the missing ABI information a separate issue?

[mpf]

I'd leave the ABI issue as a separate change or this could easily end up covering a huge amount of work.

It did occur to me that the .MIPS.abiflags data also needs updating when targetting octeon to set the isa_ext field.

Matthew

[dsanders]

In D18899#401063, @mpf wrote:

I'd leave the ABI issue as a separate change or this could easily end up covering a huge amount of work.

I've had a quick look at this and I think it's caused by the way the ABI feature bits are tied to the processor. With a mipsel-* triple we end up with half-O32 half-N64 output but it should do the right thing with a mips64el-* triple.

I think we can leave this as a separate change since MIPS64 processors on a mipsel-* triple is known to be buggy at the moment.

It did occur to me that the .MIPS.abiflags data also needs updating when targetting octeon to set the isa_ext field.

Ok, I'll add that to this patch.

[sdardis]

Flagging this as requiring changes so you see it in your queue.

[dsanders]

Implement the effect on the .MIPS.abiflags option too.
The ISA Extension field values are all mutually exclusive. Corrected the field
name accordingly.

[sdardis]

LGTM.

lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h

struct MipsABIFlagsSection {
   uint8_t ISARevision;
   // The size of general purpose registers.
   Mips::AFL_REG GPRSize;
   // The size of co-processor 1 registers.
   Mips::AFL_REG CPR1Size;
   // The size of co-processor 2 registers.
   Mips::AFL_REG CPR2Size;
   // Processor-specific extension.
-  uint32_t ISAExtensionSet;
+  Mips::AFL_EXT ISAExtension;
   // Mask of ASEs used.
   uint32_t ASESet;
 
   bool OddSPReg;
 
   bool Is32BitABI;
 
 protected:
   // The floating-point ABI.
   FpABIKind FpABI;
 
 public:
   MipsABIFlagsSection()
       : Version(0), ISALevel(0), ISARevision(0), GPRSize(Mips::AFL_REG_NONE),
         CPR1Size(Mips::AFL_REG_NONE), CPR2Size(Mips::AFL_REG_NONE),
-        ISAExtensionSet(0), ASESet(0), OddSPReg(false), Is32BitABI(false),
-        FpABI(FpABIKind::ANY) {}
+        ISAExtension(Mips::AFL_EXT_NONE), ASESet(0), OddSPReg(false),
+        Is32BitABI(false), FpABI(FpABIKind::ANY) {}
 
   uint16_t getVersionValue() { return (uint16_t)Version; }
   uint8_t getISALevelValue() { return (uint8_t)ISALevel; }
   uint8_t getISARevisionValue() { return (uint8_t)ISARevision; }
   uint8_t getGPRSizeValue() { return (uint8_t)GPRSize; }
   uint8_t getCPR1SizeValue();
   uint8_t getCPR2SizeValue() { return (uint8_t)CPR2Size; }
   uint8_t getFpABIValue();
-  uint32_t getISAExtensionSetValue() { return (uint32_t)ISAExtensionSet; }
+  uint32_t getISAExtensionValue() { return (uint32_t)ISAExtension; }
   uint32_t getASESetValue() { return (uint32_t)ASESet; }
 
   uint32_t getFlags1Value() {
     uint32_t Value = 0;
 
     if (OddSPReg)
       Value |= (uint32_t)Mips::AFL_FLAGS1_ODDSPREG;
 
if (P.useSoftFloat())
       CPR1Size = Mips::AFL_REG_NONE;
     else if (P.hasMSA())
       CPR1Size = Mips::AFL_REG_128;
     else
       CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
   }
 
   template <class PredicateLibrary>
+  void setISAExtensionFromPredicates(const PredicateLibrary &P) {
+    if (P.hasCnMips())
+      ISAExtension = Mips::AFL_EXT_OCTEON;
+    else
+      ISAExtension = Mips::AFL_EXT_NONE;
+  }
+
+  template <class PredicateLibrary>
   void setASESetFromPredicates(const PredicateLibrary &P) {
     ASESet = 0;
     if (P.hasDSP())
       ASESet |= Mips::AFL_ASE_DSP;
     if (P.hasDSPR2())
       ASESet |= Mips::AFL_ASE_DSPR2;
     if (P.hasMSA())
       ASESet |= Mips::AFL_ASE_MSA;
void setFpAbiFromPredicates(const PredicateLibrary &P) {
     }
   }
 
   template <class PredicateLibrary>
   void setAllFromPredicates(const PredicateLibrary &P) {
     setISALevelAndRevisionFromPredicates(P);
     setGPRSizeFromPredicates(P);
     setCPR1SizeFromPredicates(P);
+    setISAExtensionFromPredicates(P);
     setASESetFromPredicates(P);
     setFpAbiFromPredicates(P);
     OddSPReg = P.useOddSPReg();
   }
 };
 
 MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection);
 }
 
 #endif

lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp

uint8_t MipsABIFlagsSection::getCPR1SizeValue() {
   if (FpABI == FpABIKind::XX)
     return (uint8_t)Mips::AFL_REG_32;
   return (uint8_t)CPR1Size;
 }
 
 namespace llvm {
 MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection) {
   // Write out a Elf_Internal_ABIFlags_v0 struct
-  OS.EmitIntValue(ABIFlagsSection.getVersionValue(), 2);         // version
-  OS.EmitIntValue(ABIFlagsSection.getISALevelValue(), 1);        // isa_level
-  OS.EmitIntValue(ABIFlagsSection.getISARevisionValue(), 1);     // isa_rev
-  OS.EmitIntValue(ABIFlagsSection.getGPRSizeValue(), 1);         // gpr_size
-  OS.EmitIntValue(ABIFlagsSection.getCPR1SizeValue(), 1);        // cpr1_size
-  OS.EmitIntValue(ABIFlagsSection.getCPR2SizeValue(), 1);        // cpr2_size
-  OS.EmitIntValue(ABIFlagsSection.getFpABIValue(), 1);           // fp_abi
-  OS.EmitIntValue(ABIFlagsSection.getISAExtensionSetValue(), 4); // isa_ext
-  OS.EmitIntValue(ABIFlagsSection.getASESetValue(), 4);          // ases
-  OS.EmitIntValue(ABIFlagsSection.getFlags1Value(), 4);          // flags1
-  OS.EmitIntValue(ABIFlagsSection.getFlags2Value(), 4);          // flags2
+  OS.EmitIntValue(ABIFlagsSection.getVersionValue(), 2);      // version
+  OS.EmitIntValue(ABIFlagsSection.getISALevelValue(), 1);     // isa_level
+  OS.EmitIntValue(ABIFlagsSection.getISARevisionValue(), 1);  // isa_rev
+  OS.EmitIntValue(ABIFlagsSection.getGPRSizeValue(), 1);      // gpr_size
+  OS.EmitIntValue(ABIFlagsSection.getCPR1SizeValue(), 1);     // cpr1_size
+  OS.EmitIntValue(ABIFlagsSection.getCPR2SizeValue(), 1);     // cpr2_size
+  OS.EmitIntValue(ABIFlagsSection.getFpABIValue(), 1);        // fp_abi
+  OS.EmitIntValue(ABIFlagsSection.getISAExtensionValue(), 4); // isa_ext
+  OS.EmitIntValue(ABIFlagsSection.getASESetValue(), 4);       // ases
+  OS.EmitIntValue(ABIFlagsSection.getFlags1Value(), 4);       // flags1
+  OS.EmitIntValue(ABIFlagsSection.getFlags2Value(), 4);       // flags2
   return OS;
 }
 }

lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

else if (Features[Mips::FeatureMips32r2] ||
     EFlags |= ELF::EF_MIPS_ARCH_32R2;
   else if (Features[Mips::FeatureMips32])
     EFlags |= ELF::EF_MIPS_ARCH_32;
   else if (Features[Mips::FeatureMips2])
     EFlags |= ELF::EF_MIPS_ARCH_2;
   else
     EFlags |= ELF::EF_MIPS_ARCH_1;
 
+  // Machine
+  if (Features[Mips::FeatureCnMips])
+    EFlags |= ELF::EF_MIPS_MACH_OCTEON;
+
   // Other options.
   if (Features[Mips::FeatureNaN2008])
     EFlags |= ELF::EF_MIPS_NAN2008;
 
   // -mabicalls and -mplt are not implemented but we should act as if they were
   // given.
   EFlags |= ELF::EF_MIPS_CPIC;
 

test/MC/Mips/elf_eflags.s

 # MIPS64EL-MIPS64R2-NAN2008: Flags [ (0x80000406)
 
 # Default ABI for MIPS64 is N64 as opposed to GCC/GAS (N32)
 # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64 %s
 # MIPS64EL-MIPS64: Flags [ (0x60000006)
 
 # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-NAN2008 %s
 # MIPS64EL-MIPS64-NAN2008: Flags [ (0x60000406)
+
+# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=octeon %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-OCTEON %s
+# MIPSEL-OCTEON: Flags [ (0x808B0006)

test/MC/Mips/mips_abi_flags_xx.s

 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \
 # RUN:   FileCheck %s -check-prefix=CHECK-ASM
 #
 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
 # RUN:   llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \
-# RUN:     FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R1
+# RUN:   FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-32R1 \
+# RUN:   -check-prefix=CHECK-OBJ-MIPS
 
 # RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32 -mattr=fpxx -filetype=obj -o - | \
 # RUN:   llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \
-# RUN:     FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R1
+# RUN:   FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-32R1 \
+# RUN:   -check-prefix=CHECK-OBJ-MIPS
 
 # RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32r6 -mattr=fpxx -filetype=obj -o - | \
 # RUN:   llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \
-# RUN:     FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R6
+# RUN:   FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-32R6 \
+# RUN:   -check-prefix=CHECK-OBJ-MIPS
+
+# RUN: llvm-mc /dev/null -arch=mips -mcpu=octeon -filetype=obj -o - | \
+# RUN:   llvm-readobj -sections -section-data -section-relocations -mips-abi-flags - | \
+# RUN:   FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-64R2 \
+# RUN:   -check-prefix=CHECK-OBJ-OCTEON
 
 # CHECK-ASM: .module fp=xx
 
 # Checking if the Mips.abiflags were correctly emitted.
 # CHECK-OBJ:       Section {
 # CHECK-OBJ:         Index: 5
-# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags (12)
+# CHECK-OBJ-LABEL:   Name: .MIPS.abiflags
 # CHECK-OBJ:         Type: SHT_MIPS_ABIFLAGS (0x7000002A)
 # CHECK-OBJ:          Flags [ (0x2)
 # CHECK-OBJ:           SHF_ALLOC (0x2)
 # CHECK-OBJ:         ]
 # CHECK-OBJ:         Address: 0x0
 # CHECK-OBJ:         Size: 24
 # CHECK-OBJ:         Link: 0
 # CHECK-OBJ:         Info: 0
 # CHECK-OBJ:         AddressAlignment: 8
 # CHECK-OBJ:         EntrySize: 24
 # CHECK-OBJ:         Relocations [
 # CHECK-OBJ:         ]
 # CHECK-OBJ-LABEL: }
 # CHECK-OBJ:       MIPS ABI Flags {
 # CHECK-OBJ-NEXT:    Version: 0
-# CHECK-OBJ-R1-NEXT: ISA: {{MIPS32$}}
-# CHECK-OBJ-R6-NEXT: ISA: MIPS32r6
-# CHECK-OBJ-NEXT:    ISA Extension: None (0x0)
-# CHECK-OBJ-NEXT:    ASEs [ (0x0)
-# CHECK-OBJ-NEXT:    ]
-# CHECK-OBJ-NEXT:    FP ABI: Hard float (32-bit CPU, Any FPU) (0x5)
-# CHECK-OBJ-NEXT:    GPR size: 32
-# CHECK-OBJ-NEXT:    CPR1 size: 32
+# CHECK-OBJ-32R1-NEXT: ISA: {{MIPS32$}}
+# CHECK-OBJ-32R6-NEXT: ISA: MIPS32r6
+# CHECK-OBJ-64R2-NEXT: ISA: MIPS64r2
+# CHECK-OBJ-MIPS-NEXT:   ISA Extension: None (0x0)
+# CHECK-OBJ-OCTEON-NEXT: ISA Extension: Cavium Networks Octeon (0x5)
+# CHECK-OBJ-NEXT:    ASEs [ (0x0)          
+# CHECK-OBJ-NEXT:    ]                     
+# CHECK-OBJ-32R1-NEXT: FP ABI: Hard float (32-bit CPU, Any FPU) (0x5)
+# CHECK-OBJ-32R6-NEXT: FP ABI: Hard float (32-bit CPU, Any FPU) (0x5)
+# CHECK-OBJ-64R2-NEXT: FP ABI: Hard float (double precision) (0x1)
+# CHECK-OBJ-32R1-NEXT: GPR size: 32
+# CHECK-OBJ-32R6-NEXT: GPR size: 32
+# CHECK-OBJ-64R2-NEXT: GPR size: 64
+# CHECK-OBJ-32R1-NEXT: CPR1 size: 32
+# CHECK-OBJ-32R6-NEXT: CPR1 size: 32
+# CHECK-OBJ-64R2-NEXT: CPR1 size: 64
 # CHECK-OBJ-NEXT:    CPR2 size: 0
 # CHECK-OBJ-NEXT:    Flags 1 [ (0x1)
 # CHECK-OBJ-NEXT:      ODDSPREG (0x1)
 # CHECK-OBJ-NEXT:    ]
 # CHECK-OBJ-NEXT:    Flags 2: 0x0
 # CHECK-OBJ-NEXT:  }
 
         .module fp=xx
 
 # FIXME: Test should include gnu_attributes directive when implemented.
 #        An explicit .gnu_attribute must be checked against the effective
 #        command line options and any inconsistencies reported via a warning.