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Differential D18659

[AMDGPU] fix MADAK/MADMK instructions operand namings.
ClosedPublic

Authored by vpykhtin on Mar 31 2016, 11:22 AM.

Details

Reviewers
• tstellarAMD
arsenm
Commits
rG5b3559c1ecd9: [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.
rL265141: [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.
Summary

$vsrc1 -> $src1, $k -> $imm

Diff Detail

Repository
rL LLVM

Event Timeline

vpykhtin updated this revision to Diff 52246.Mar 31 2016, 11:22 AM
vpykhtin retitled this revision from to [AMDGPU] fix MADAK/MADMK instructions operand namings..
vpykhtin updated this object.
vpykhtin added reviewers: • tstellarAMD, arsenm.
Herald added a subscriber: arsenm. · View Herald TranscriptMar 31 2016, 11:22 AM
Closed by commit rL265141: [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields. (authored by vpykhtin). · Explain WhyApr 1 2016, 6:18 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
8 lines
8 lines
test/
MC/
Disassembler/
AMDGPU/
16 lines

Diff 52359

llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td

Show First 20 Lines • Show All 363 Lines • ▼ Show 20 Linesclass VOP2e <bits<6> op> : Enc32 {
let Inst{30-25} = op; let Inst{30-25} = op;
let Inst{31} = 0x0; //encoding let Inst{31} = 0x0; //encoding
} }
class VOP2_MADKe <bits<6> op> : Enc64 { class VOP2_MADKe <bits<6> op> : Enc64 {
bits<8> vdst; bits<8> vdst;
bits<9> src0; bits<9> src0;
bits<8> vsrc1; bits<8> src1;
bits<32> src2; bits<32> imm;
let Inst{8-0} = src0; let Inst{8-0} = src0;
let Inst{16-9} = vsrc1; let Inst{16-9} = src1;
let Inst{24-17} = vdst; let Inst{24-17} = vdst;
let Inst{30-25} = op; let Inst{30-25} = op;
let Inst{31} = 0x0; // encoding let Inst{31} = 0x0; // encoding
let Inst{63-32} = src2; let Inst{63-32} = imm;
} }
class VOP3a <bits<9> op> : Enc64 { class VOP3a <bits<9> op> : Enc64 {
bits<2> src0_modifiers; bits<2> src0_modifiers;
bits<9> src0; bits<9> src0;
bits<2> src1_modifiers; bits<2> src1_modifiers;
bits<9> src1; bits<9> src1;
bits<2> src2_modifiers; bits<2> src2_modifiers;
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llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

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def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> { def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2); let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
let Asm64 = "$vdst, $src0, $src1, $src2"; let Asm64 = "$vdst, $src0, $src1, $src2";
} }
def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>; def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
def VOP_MADAK : VOPProfile <[f32, f32, f32, f32]> { def VOP_MADAK : VOPProfile <[f32, f32, f32, f32]> {
field dag Ins32 = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$k); field dag Ins32 = (ins VCSrc_32:$src0, VGPR_32:$src1, u32imm:$imm);
field string Asm32 = "$vdst, $src0, $vsrc1, $k"; field string Asm32 = "$vdst, $src0, $src1, $imm";
} }
def VOP_MADMK : VOPProfile <[f32, f32, f32, f32]> { def VOP_MADMK : VOPProfile <[f32, f32, f32, f32]> {
field dag Ins32 = (ins VCSrc_32:$src0, u32imm:$k, VGPR_32:$vsrc1); field dag Ins32 = (ins VCSrc_32:$src0, u32imm:$imm, VGPR_32:$src1);
field string Asm32 = "$vdst, $src0, $k, $vsrc1"; field string Asm32 = "$vdst, $src0, $imm, $src1";
} }
def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> { def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2); let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3, let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
HasModifiers>.ret; HasModifiers>.ret;
let InsDPP = (ins InputModsNoDefault:$src0_modifiers, Src0RC32:$src0, let InsDPP = (ins InputModsNoDefault:$src0_modifiers, Src0RC32:$src0,
InputModsNoDefault:$src1_modifiers, Src1RC32:$src1, InputModsNoDefault:$src1_modifiers, Src1RC32:$src1,
VGPR_32:$src2, // stub argument VGPR_32:$src2, // stub argument
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llvm/trunk/test/MC/Disassembler/AMDGPU/vop2_vi.txt

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0x02 0x07 0x02 0x2a 0x02 0x07 0x02 0x2a
# VI: v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x93,0xd2,0x02,0x07,0x02,0x00] # VI: v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x93,0xd2,0x02,0x07,0x02,0x00]
0x01 0x00 0x93 0xd2 0x02 0x07 0x02 0x00 0x01 0x00 0x93 0xd2 0x02 0x07 0x02 0x00
# VI: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c] # VI: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
0x02 0x07 0x02 0x2c 0x02 0x07 0x02 0x2c
# FIXME: v_madmk_f32_e32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x2e,0x00,0x00,0x80,0x42] # VI: v_madmk_f32_e32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x2e,0x00,0x00,0x80,0x42]
#0x02 0x07 0x02 0x2e 0x00 0x00 0x80 0x42 0x02 0x07 0x02 0x2e 0x00 0x00 0x80 0x42
# FIXME: v_madak_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x30,0x00,0x00,0x80,0x42] # VI: v_madak_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x30,0x00,0x00,0x80,0x42]
#0x02 0x07 0x02 0x30 0x00 0x00 0x80 0x42 0x02 0x07 0x02 0x30 0x00 0x00 0x80 0x42
# VI: v_bcnt_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8b,0xd2,0x02,0x07,0x02,0x00] # VI: v_bcnt_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8b,0xd2,0x02,0x07,0x02,0x00]
0x01 0x00 0x8b 0xd2 0x02 0x07 0x02 0x00 0x01 0x00 0x8b 0xd2 0x02 0x07 0x02 0x00
# VI: v_mbcnt_lo_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8c,0xd2,0x02,0x07,0x02,0x00] # VI: v_mbcnt_lo_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8c,0xd2,0x02,0x07,0x02,0x00]
0x01 0x00 0x8c 0xd2 0x02 0x07 0x02 0x00 0x01 0x00 0x8c 0xd2 0x02 0x07 0x02 0x00
# VI: v_mbcnt_hi_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8d,0xd2,0x02,0x07,0x02,0x00] # VI: v_mbcnt_hi_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x8d,0xd2,0x02,0x07,0x02,0x00]
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0x02 0x07 0x02 0x42 0x02 0x07 0x02 0x42
# VI: v_mul_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44] # VI: v_mul_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
0x02 0x07 0x02 0x44 0x02 0x07 0x02 0x44
# VI: v_mac_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46] # VI: v_mac_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46]
0x02 0x07 0x02 0x46 0x02 0x07 0x02 0x46
# FIXME: v_madmk_f16_e32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x48,0x00,0x00,0x80,0x42] # VI: v_madmk_f16_e32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x48,0x00,0x00,0x80,0x42]
#0x02 0x07 0x02 0x48 0x00 0x00 0x80 0x42 0x02 0x07 0x02 0x48 0x00 0x00 0x80 0x42
# FIXME: v_madak_f16_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x4a,0x00,0x00,0x80,0x42] # VI: v_madak_f16_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x4a,0x00,0x00,0x80,0x42]
#0x02 0x07 0x02 0x4a 0x00 0x00 0x80 0x42 0x02 0x07 0x02 0x4a 0x00 0x00 0x80 0x42
# VI: v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c] # VI: v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
0x02 0x07 0x02 0x4c 0x02 0x07 0x02 0x4c
# VI: v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e] # VI: v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
0x02 0x07 0x02 0x4e 0x02 0x07 0x02 0x4e
# VI: v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50] # VI: v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50]
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