This includes a hazard recognizer implementation to replace some of
the hazard handling we had during frame index elimination.
Details
Diff Detail
- Repository
- rL LLVM
Event Timeline
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | ||
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375 ↗ | (On Diff #52066) | Where is this added? |
lib/Target/AMDGPU/GCNHazardRecognizer.cpp | ||
40–46 ↗ | (On Diff #52066) | It seems RegDefs isn't actually used anywhere? |
116–117 ↗ | (On Diff #52066) | Are you sure this does the right thing? According to the comment, definesRegister only returns true if the instruction defines a super-register of Reg, but there is probably also a hazard if it defines a sub-register. |
lib/Target/AMDGPU/SIInstrInfo.cpp | ||
1198 ↗ | (On Diff #52066) | Typo: ds_read2 |
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | ||
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375 ↗ | (On Diff #52066) | |
lib/Target/AMDGPU/GCNHazardRecognizer.cpp | ||
116–117 ↗ | (On Diff #52066) | I think to correctly handle physical registers I should be using 'modifiesReigster' instead of 'definesRegister'. For virtual registers the two functions behave the same, and I think this is OK, because when sub-registers are defined by an operand, MO.getReg() will return the super-register and not the sub-register. So MI->defineRegister(Reg) will return true if MI defines a sub-reg of Reg. |
Use MI->modifiesRegister instead of definesRegister. Also move most of
the EmitInstruction() code into AdvanceCycle() which better matches
how the hazard recognizer is used by the scheduler.
lib/Target/AMDGPU/GCNHazardRecognizer.cpp | ||
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107 ↗ | (On Diff #52937) | Typo recogiznizer |
138–139 ↗ | (On Diff #52937) | A comment about why SI only would be helpful |
lib/Target/AMDGPU/GCNHazardRecognizer.h | ||
18–21 ↗ | (On Diff #52937) | I think only <list> is needed here. The others aren't used or can be moved into the cpp file |
30 ↗ | (On Diff #52937) | final |
32 ↗ | (On Diff #52937) | Typo: variabled |
47 ↗ | (On Diff #52937) | Grammar: instruction be cycle |
lib/Target/AMDGPU/SIInstrInfo.cpp | ||
828 ↗ | (On Diff #52937) | line break |