Add MachineFunctionProperty checks for AllVRegsAllocated for target passes

[dschuff]

Summary

This adds the same checks that were added in r264593 to all
target-specific passes that run after register allocation.

These passes declare that the passes assume that there will
never be virtual register register operands, and the
MachineFunctionPass now enforces this check.

[qcolombet]

Hi Derek,

LGTM.

Thanks,
Q.

llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp

public:
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesAll();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   const char *getPassName() const override {
     return "Execution dependency fix";
   }
 
 private:
   iterator_range<SmallVectorImpl<int>::const_iterator>
   regIndices(unsigned Reg) const;
 

llvm/trunk/lib/CodeGen/IfConversion.cpp

public:
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineBlockFrequencyInfo>();
       AU.addRequired<MachineBranchProbabilityInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
   private:
     bool ReverseBranchCondition(BBInfo &BBI);
     bool ValidSimple(BBInfo &TrueBBI, unsigned &Dups,
                      BranchProbability Prediction) const;
     bool ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI,
                        bool FalseBranch, unsigned &Dups,
                        BranchProbability Prediction) const;
     bool ValidDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,

llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp

class AArch64A53Fix835769 : public MachineFunctionPass {
   const TargetInstrInfo *TII;
 
 public:
   static char ID;
   explicit AArch64A53Fix835769() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   const char *getPassName() const override {
     return "Workaround A53 erratum 835769 pass";
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }

llvm/trunk/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

 public:
   static char ID;
   explicit AArch64A57FPLoadBalancing() : MachineFunctionPass(ID) {
     initializeAArch64A57FPLoadBalancingPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   const char *getPassName() const override {
     return "A57 FP Anti-dependency breaker";
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }

llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp

 struct AArch64CollectLOH : public MachineFunctionPass {
   static char ID;
   AArch64CollectLOH() : MachineFunctionPass(ID) {
     initializeAArch64CollectLOHPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   const char *getPassName() const override {
     return AARCH64_COLLECT_LOH_NAME;
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesAll();
     MachineFunctionPass::getAnalysisUsage(AU);
     AU.addRequired<MachineDominatorTree>();

llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp

public:
   static char ID; // Pass identification, replacement for typeid.
   explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
     initializeAArch64DeadRegisterDefinitionsPass(
         *PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   const char *getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 };
 char AArch64DeadRegisterDefinitions::ID = 0;

llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

struct AArch64LoadStoreOpt : public MachineFunctionPass {
   // Check if converting two narrow loads into a single wider load with
   // bitfield extracts could be enabled.
   bool enableNarrowLdMerge(MachineFunction &Fn);
 
   bool optimizeBlock(MachineBasicBlock &MBB, bool enableNarrowLdOpt);
 
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   const char *getPassName() const override {
     return AARCH64_LOAD_STORE_OPT_NAME;
   }
 };
 char AArch64LoadStoreOpt::ID = 0;
 } // namespace
 
 INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",

llvm/trunk/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

class AArch64RedundantCopyElimination : public MachineFunctionPass {
   const MachineRegisterInfo *MRI;
   const TargetRegisterInfo *TRI;
 
 public:
   static char ID;
   AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {}
   bool optimizeCopy(MachineBasicBlock *MBB);
   bool runOnMachineFunction(MachineFunction &MF) override;
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
   const char *getPassName() const override {
     return "AArch64 Redundant Copy Elimination";
   }
 };
 char AArch64RedundantCopyElimination::ID = 0;
 }
 
 INITIALIZE_PASS(AArch64RedundantCopyElimination, "aarch64-copyelim",

llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp

class ARMConstantIslands : public MachineFunctionPass {
     bool isThumb1;
     bool isThumb2;
   public:
     static char ID;
     ARMConstantIslands() : MachineFunctionPass(ID) {}
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     const char *getPassName() const override {
       return "ARM constant island placement and branch shortening pass";
     }
 
   private:
     void doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs);
     void doInitialJumpTablePlacement(std::vector<MachineInstr *> &CPEMIs);
     bool BBHasFallthrough(MachineBasicBlock *MBB);

llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp

public:
 
     const ARMBaseInstrInfo *TII;
     const TargetRegisterInfo *TRI;
     const ARMSubtarget *STI;
     ARMFunctionInfo *AFI;
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     const char *getPassName() const override {
       return "ARM pseudo instruction expansion pass";
     }
 
   private:
     void TransferImpOps(MachineInstr &OldMI,
                         MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
     bool ExpandMI(MachineBasicBlock &MBB,

llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

struct ARMLoadStoreOpt : public MachineFunctionPass {
     RegisterClassInfo RegClassInfo;
     MachineBasicBlock::const_iterator LiveRegPos;
     bool LiveRegsValid;
     bool RegClassInfoValid;
     bool isThumb1, isThumb2;
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     const char *getPassName() const override {
       return ARM_LOAD_STORE_OPT_NAME;
     }
 
   private:
     /// A set of load/store MachineInstrs with same base register sorted by
     /// offset.
     struct MemOpQueueEntry {

 
 
 /// Returns an instance of the load / store optimization pass.
 FunctionPass *llvm::createARMLoadStoreOptimizationPass(bool PreAlloc) {
   if (PreAlloc)
     return new ARMPreAllocLoadStoreOpt();
   return new ARMLoadStoreOpt();
 }
-

llvm/trunk/lib/Target/ARM/ARMOptimizeBarriersPass.cpp

 namespace {
 class ARMOptimizeBarriersPass : public MachineFunctionPass {
 public:
   static char ID;
   ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   const char *getPassName() const override {
     return "optimise barriers pass";
   }
 };
 char ARMOptimizeBarriersPass::ID = 0;
 }
 
 // Returns whether the instruction can safely move past a DMB instruction

llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp

public:
 
     bool restrictIT;
     const Thumb2InstrInfo *TII;
     const TargetRegisterInfo *TRI;
     ARMFunctionInfo *AFI;
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     const char *getPassName() const override {
       return "Thumb IT blocks insertion pass";
     }
 
   private:
     bool MoveCopyOutOfITBlock(MachineInstr *MI,
                               ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
                               SmallSet<unsigned, 4> &Defs,

llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

public:
     static char ID;
     Thumb2SizeReduce(std::function<bool(const Function &)> Ftor);
 
     const Thumb2InstrInfo *TII;
     const ARMSubtarget *STI;
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     const char *getPassName() const override {
       return "Thumb2 instruction size reduction pass";
     }
 
   private:
     /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
     DenseMap<unsigned, unsigned> ReduceOpcodeMap;
 

llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp

public:
   HexagonCFGOptimizer() : MachineFunctionPass(ID) {
     initializeHexagonCFGOptimizerPass(*PassRegistry::getPassRegistry());
   }
 
   const char *getPassName() const override {
     return "Hexagon CFG Optimizer";
   }
   bool runOnMachineFunction(MachineFunction &Fn) override;
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
 };
 
 
 char HexagonCFGOptimizer::ID = 0;
 
 static bool IsConditionalBranch(int Opc) {
   return (Opc == Hexagon::J2_jumpt) || (Opc == Hexagon::J2_jumpf)
     || (Opc == Hexagon::J2_jumptnewpt) || (Opc == Hexagon::J2_jumpfnewpt);

llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp

public:
   }
 
   const char *getPassName() const override {
     return "Hexagon Copy-To-Combine Pass";
   }
 
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
 private:
   MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1,
                              bool AllowC64);
 
   void findPotentialNewifiableTFRs(MachineBasicBlock &);
 
   void combine(MachineInstr *I1, MachineInstr *I2,
                MachineBasicBlock::iterator &MI, bool DoInsertAtI1,

llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp

public:
     static char ID;
 
     HexagonFixupHwLoops() : MachineFunctionPass(ID) {
       initializeHexagonFixupHwLoopsPass(*PassRegistry::getPassRegistry());
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     const char *getPassName() const override {
       return "Hexagon Hardware Loop Fixup";
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
     }

llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp

namespace {
   class HexagonCallFrameInformation : public MachineFunctionPass {
   public:
     static char ID;
     HexagonCallFrameInformation() : MachineFunctionPass(ID) {
       PassRegistry &PR = *PassRegistry::getPassRegistry();
       initializeHexagonCallFrameInformationPass(PR);
     }
     bool runOnMachineFunction(MachineFunction &MF) override;
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
   };
 
   char HexagonCallFrameInformation::ID = 0;
 }
 
 bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
   auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
   bool NeedCFI = MF.getMMI().hasDebugInfo() ||

llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp

public:
     }
     const char *getPassName() const override {
       return "Hexagon generate mux instructions";
     }
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
     bool runOnMachineFunction(MachineFunction &MF) override;
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
 
   private:
     const HexagonInstrInfo *HII;
     const HexagonRegisterInfo *HRI;
 
     struct CondsetInfo {
       unsigned PredR;
       unsigned TrueX, FalseX;
bool HexagonGenMux::runOnMachineFunction(MachineFunction &MF) {
   for (auto &I : MF)
     Changed |= genMuxInBlock(I);
   return Changed;
 }
 
 FunctionPass *llvm::createHexagonGenMux() {
   return new HexagonGenMux();
 }
-

llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
     const char *getPassName() const override {
       return "Hexagon NewValueJump";
     }
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
 
   private:
     /// \brief A handle to the branch probability pass.
     const MachineBranchProbabilityInfo *MBPI;
 
     bool isNewValueJumpCandidate(const MachineInstr *MI) const;
   };
 

llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesAll();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
     const char *getPassName() const override {
       return "Hexagon RDF optimizations";
     }
     bool runOnMachineFunction(MachineFunction &MF) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     static char ID;
 
   private:
     MachineDominatorTree *MDT;
     MachineRegisterInfo *MRI;
   };
 
   char HexagonRDFOpt::ID = 0;

llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp

  public:
     static char ID;
     HexagonSplitConst32AndConst64() : MachineFunctionPass(ID) {}
 
     const char *getPassName() const override {
       return "Hexagon Split Const32s and Const64s";
     }
     bool runOnMachineFunction(MachineFunction &Fn) override;
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
 };
 
 
 char HexagonSplitConst32AndConst64::ID = 0;
 
 
 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
 

llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addPreserved<MachineDominatorTree>();
       AU.addPreserved<MachineLoopInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
     const char *getPassName() const override {
       return "Hexagon Packetizer";
     }
     bool runOnMachineFunction(MachineFunction &Fn) override;
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
 
   private:
     const HexagonInstrInfo *HII;
     const HexagonRegisterInfo *HRI;
   };
 
   char HexagonPacketizer::ID = 0;
 }

 
 //===----------------------------------------------------------------------===//
 //                         Public Constructor Functions
 //===----------------------------------------------------------------------===//
 
 FunctionPass *llvm::createHexagonPacketizer() {
   return new HexagonPacketizer();
 }
-

llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp

bool runOnMachineFunction(MachineFunction &MF) override {
 
     bool Changed = false;
     for (MachineFunction::iterator FI = MF.begin(), FE = MF.end(); FI != FE;
          ++FI)
       Changed |= runOnMachineBasicBlock(*FI);
     return Changed;
   }
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   void insertDefsUses(MachineBasicBlock::instr_iterator MI,
                       SmallSet<unsigned, 32> &RegDefs,
                       SmallSet<unsigned, 32> &RegUses);
 
   bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
 
   bool delayHasHazard(MachineBasicBlock::instr_iterator MI, bool &SawLoad,
                       bool &SawStore, SmallSet<unsigned, 32> &RegDefs,

llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp

public:
   }
 
   const char *getPassName() const override {
     return "Lanai load / store optimization pass";
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
 private:
   MbbIterator findClosestSuitableAluInstr(MachineBasicBlock *BB,
                                           const MbbIterator &MemInstr,
                                           bool Decrement);
   void insertMergedInstruction(MachineBasicBlock *BB,
                                const MbbIterator &MemInstr,
                                const MbbIterator &AluInstr, bool Before);
   bool combineMemAluInBasicBlock(MachineBasicBlock *BB);

llvm/trunk/lib/Target/Lanai/LanaiSetflagAluCombiner.cpp

public:
   }
 
   const char *getPassName() const override {
     return "Lanai SET_FLAG ALU combiner pass";
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
 private:
   bool CombineSetflagAluInBasicBlock(MachineFunction *MF,
                                      MachineBasicBlock *BB);
 };
 } // namespace
 
 char LanaiSetflagAluCombiner::ID = 0;
 

llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp

struct MSP430BSel : public MachineFunctionPass {
     static char ID;
     MSP430BSel() : MachineFunctionPass(ID) {}
 
     /// BlockSizes - The sizes of the basic blocks in the function.
     std::vector<unsigned> BlockSizes;
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     const char *getPassName() const override {
       return "MSP430 Branch Selector";
     }
   };
   char MSP430BSel::ID = 0;
 }
 
 /// createMSP430BranchSelectionPass - returns an instance of the Branch

llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp

MipsConstantIslands(TargetMachine &tm)
           MF(nullptr), MCP(nullptr), PrescannedForConstants(false) {}
 
     const char *getPassName() const override {
       return "Mips Constant Islands";
     }
 
     bool runOnMachineFunction(MachineFunction &F) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs);
     CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
     unsigned getCPELogAlign(const MachineInstr *CPEMI);
     void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
     unsigned getOffsetOf(MachineInstr *MI) const;
     unsigned getUserOffset(CPUser&) const;
     void dumpBBs();
 
for (MachineBasicBlock::instr_iterator I =
           break;
         }
         default:
           break;
       }
     }
   }
 }
-

llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp

bool runOnMachineFunction(MachineFunction &F) override {
       // instructions to fill delay slot. Without this, -verify-machineinstrs
       // will fail.
       if (Changed)
         F.getRegInfo().invalidateLiveness();
 
       return Changed;
     }
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineBranchProbabilityInfo>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
   private:
     bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
 

llvm/trunk/lib/Target/Mips/MipsHazardSchedule.cpp

 
 public:
   MipsHazardSchedule() : MachineFunctionPass(ID) {}
 
   const char *getPassName() const override { return "Mips Hazard Schedule"; }
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
 private:
   static char ID;
 };
 
 char MipsHazardSchedule::ID = 0;
 } // end of anonymous namespace
 
 /// Returns a pass that clears pipeline hazards.

llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp

MipsLongBranch(TargetMachine &tm)
           ABI(static_cast<const MipsTargetMachine &>(TM).getABI()) {}
 
     const char *getPassName() const override {
       return "Mips Long Branch";
     }
 
     bool runOnMachineFunction(MachineFunction &F) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
   private:
     void splitMBB(MachineBasicBlock *MBB);
     void initMBBInfo();
     int64_t computeOffset(const MachineInstr *Br);
     void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
                        MachineBasicBlock *MBBOpnd);
     void expandToLongBranch(MBBInfo &Info);
 

llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp

PPCBSel() : MachineFunctionPass(ID) {
       initializePPCBSelPass(*PassRegistry::getPassRegistry());
     }
 
     /// BlockSizes - The sizes of the basic blocks in the function.
     std::vector<unsigned> BlockSizes;
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     const char *getPassName() const override {
       return "PowerPC Branch Selector";
     }
   };
   char PPCBSel::ID = 0;
 }
 
 INITIALIZE_PASS(PPCBSel, "ppc-branch-select", "PowerPC Branch Selector",
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
       }
     }
     EverMadeChange |= MadeChange;
   }
   
   BlockSizes.clear();
   return true;
 }
-

llvm/trunk/lib/Target/PowerPC/PPCEarlyReturn.cpp

bool runOnMachineFunction(MachineFunction &MF) override {
         MachineBasicBlock &B = *I++;
         if (processBlock(B))
           Changed = true;
       }
 
       return Changed;
     }
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
   };
 }
 
 INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
                 "PowerPC Early-Return Creation", false, false)
 
 char PPCEarlyReturn::ID = 0;
 FunctionPass*
 llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }
-

llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp

bool runOnMachineFunction(MachineFunction &F) override {
       F.getRegInfo().invalidateLiveness();
 
       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
            FI != FE; ++FI)
         Changed |= runOnMachineBasicBlock(*FI);
       return Changed;
     }
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     void insertCallDefsUses(MachineBasicBlock::iterator MI,
                             SmallSet<unsigned, 32>& RegDefs,
                             SmallSet<unsigned, 32>& RegUses);
 
     void insertDefsUses(MachineBasicBlock::iterator MI,
                         SmallSet<unsigned, 32>& RegDefs,
                         SmallSet<unsigned, 32>& RegUses);
 

llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp

SystemZElimCompare(const SystemZTargetMachine &tm)
     : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr) {}
 
   const char *getPassName() const override {
     return "SystemZ Comparison Elimination";
   }
 
   bool processBlock(MachineBasicBlock &MBB);
   bool runOnMachineFunction(MachineFunction &F) override;
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
 
 private:
   Reference getRegReferences(MachineInstr *MI, unsigned Reg);
   bool convertToBRCT(MachineInstr *MI, MachineInstr *Compare,
                      SmallVectorImpl<MachineInstr *> &CCUsers);
   bool convertToLoadAndTest(MachineInstr *MI);
   bool adjustCCMasksForInstr(MachineInstr *MI, MachineInstr *Compare,
                              SmallVectorImpl<MachineInstr *> &CCUsers);

llvm/trunk/lib/Target/SystemZ/SystemZLongBranch.cpp

public:
   SystemZLongBranch(const SystemZTargetMachine &tm)
     : MachineFunctionPass(ID), TII(nullptr) {}
 
   const char *getPassName() const override {
     return "SystemZ Long Branch";
   }
 
   bool runOnMachineFunction(MachineFunction &F) override;
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
 
 private:
   void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);
   void skipTerminator(BlockPosition &Position, TerminatorInfo &Terminator,
                       bool AssumeRelaxed);
   TerminatorInfo describeTerminator(MachineInstr *MI);
   uint64_t initMBBInfo();
   bool mustRelaxBranch(const TerminatorInfo &Terminator, uint64_t Address);

llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp

public:
   SystemZShortenInst(const SystemZTargetMachine &tm);
 
   const char *getPassName() const override {
     return "SystemZ Instruction Shortening";
   }
 
   bool processBlock(MachineBasicBlock &MBB);
   bool runOnMachineFunction(MachineFunction &F) override;
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
 
 private:
   bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
   bool shortenOn0(MachineInstr &MI, unsigned Opcode);
   bool shortenOn01(MachineInstr &MI, unsigned Opcode);
   bool shortenOn001(MachineInstr &MI, unsigned Opcode);
   bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
   bool shortenFPConv(MachineInstr &MI, unsigned Opcode);

llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp

public:
 
   const X86Subtarget *STI;
   const X86InstrInfo *TII;
   const X86RegisterInfo *TRI;
   const X86FrameLowering *X86FL;
 
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   const char *getPassName() const override {
     return "X86 pseudo instruction expansion pass";
   }
 
 private:
   bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
   bool ExpandMBB(MachineBasicBlock &MBB);
 };

llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   /// \brief Loop over all of the basic blocks,
   /// replacing byte and word instructions by equivalent 32 bit instructions
   /// where performance or code size can be improved.
   bool runOnMachineFunction(MachineFunction &MF) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
 private:
   MachineFunction *MF;
 
   /// Machine instruction info used throughout the class.
   const X86InstrInfo *TII;
 
   /// Local member for function's OptForSize attribute.
   bool OptForSize;

llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp

 public:
   FixupLEAPass() : MachineFunctionPass(ID) {}
 
   /// \brief Loop over all of the basic blocks,
   /// replacing instructions by equivalent LEA instructions
   /// if needed and when possible.
   bool runOnMachineFunction(MachineFunction &MF) override;
 
+  // This pass runs after regalloc and doesn't support VReg operands.
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
 private:
   MachineFunction *MF;
   const X86InstrInfo *TII; // Machine instruction info.
   bool OptIncDec;
   bool OptLEA;
 };
 char FixupLEAPass::ID = 0;
 }

llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<EdgeBundles>();
       AU.addPreservedID(MachineLoopInfoID);
       AU.addPreservedID(MachineDominatorsID);
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     const char *getPassName() const override { return "X86 FP Stackifier"; }
 
   private:
     const TargetInstrInfo *TII; // Machine instruction info.
 
     // Two CFG edges are related if they leave the same block, or enter the same
     // block. The transitive closure of an edge under this relation is a
     // LiveBundle. It represents a set of CFG edges where the live FP stack

llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp

namespace {
 
   struct PadShortFunc : public MachineFunctionPass {
     static char ID;
     PadShortFunc() : MachineFunctionPass(ID)
                    , Threshold(4), STI(nullptr), TII(nullptr) {}
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
+
     const char *getPassName() const override {
       return "X86 Atom pad short functions";
     }
 
   private:
     void findReturns(MachineBasicBlock *MBB,
                      unsigned int Cycles = 0);
 

llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp

 
 namespace {
 
   class VZeroUpperInserter : public MachineFunctionPass {
   public:
 
     VZeroUpperInserter() : MachineFunctionPass(ID) {}
     bool runOnMachineFunction(MachineFunction &MF) override;
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
     const char *getPassName() const override {return "X86 vzeroupper inserter";}
 
   private:
 
     void processBasicBlock(MachineBasicBlock &MBB);
     void insertVZeroUpper(MachineBasicBlock::iterator I,
                           MachineBasicBlock &MBB);
     void addDirtySuccessor(MachineBasicBlock &MBB);

llvm/trunk/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp

 using namespace llvm;
 
 namespace {
   struct XCoreFTAOElim : public MachineFunctionPass {
     static char ID;
     XCoreFTAOElim() : MachineFunctionPass(ID) {}
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::AllVRegsAllocated);
+    }
 
     const char *getPassName() const override {
       return "XCore FRAME_TO_ARGS_OFFSET Elimination";
     }
   };
   char XCoreFTAOElim::ID = 0;
 }
 

llvm/trunk/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir

--- |
   !34 = !DILocation(line: 15, scope: !4)
 
 ...
 ---
 name:            f
 alignment:       1
 exposesReturnsTwice: false
 hasInlineAsm:    false
+allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
 liveins:         
   - { reg: '%r0' }
   - { reg: '%r2' }
   - { reg: '%r3' }
 calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',