CodeGen: Correct specification of PHI nodes

[MatzeB]

Summary

They do have a def machine operand.

Fixing the definition is necessary for an upcoming patch.

[MatzeB]

I am posting this for review, because I did not expect the change in the AMDGPU test being necessary.

It would be nice if someone familiar with AMDGPU could double check the AMDGPU testcase change. Looking through the AMDGPU code my guess would be that SIFixSGPRLiveRanges.cpp missed PHI instruction definitions before this patch, as the phi def operands where not part of the MachineInstr::defs() iterator before this fix.

Reading the comment in that code, I'd also recommend to change the code to loop over all MachineInstr::operands(), there is nothing preventing implicit-defs to address vregs as well (though this may not happen in the AMDGPU backend today).

[• tstellarAMD]

Thanks for diagnosing the issue with the AMDGPU backend. I don't think I'm going to have time to look into this in the next few days, so I don't mind dealing with any problems in a post-commit review. You can commit when ready.

llvm/trunk/include/llvm/Target/Target.td

 }
 
 // Standard Pseudo Instructions.
 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
 // Only these instructions are allowed in the TargetOpcode namespace.
 let isCodeGenOnly = 1, isPseudo = 1, hasNoSchedulingInfo = 1,
     Namespace = "TargetOpcode" in {
 def PHI : Instruction {
-  let OutOperandList = (outs);
+  let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins variable_ops);
   let AsmString = "PHINODE";
 }
 def INLINEASM : Instruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "";
   let hasSideEffects = 0;  // Note side effect is encoded in an operand.

llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll

 ; SI: s_and_b64 [[ORNEG1:s\[[0-9]+:[0-9]+\]]], [[NEG1_CHECK_1]], [[NEG1_CHECK_0]]
 ; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]]
 ; SI: s_xor_b64 [[ORNEG2]], exec, [[ORNEG2]]
 ; SI: s_cbranch_execz BB3_5
 
 ; SI: BB#4:
 ; SI: buffer_store_dword
 ; SI: v_cmp_ge_i64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]]
-; SI: s_or_b64 [[COND_STATE]], [[CMP]], [[COND_STATE]]
+; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]]
 
 ; SI: BB3_5:
 ; SI: s_or_b64 exec, exec, [[ORNEG2]]
-; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[COND_STATE]]
+; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[TMP]]
 ; SI: s_andn2_b64 exec, exec, [[COND_STATE]]
 ; SI: s_cbranch_execnz BB3_3
 
 ; SI: BB#6
 ; SI: s_or_b64 exec, exec, [[COND_STATE]]
 
 ; SI: BB3_2:
 ; SI-NOT: [[COND_STATE]]