[mips] Correct MIPS16 jal/jalx to have uimm26 offsets and add MC layer range checks. NFC.

[dsanders]

Summary

However, this has no effect at this time because the instructions affected
are marked 'isCodeGenOnly=1' and have no alternative for the MC layer.

[vkalintiris]

LGTM. I was going to ask for few test cases, as you've done with the previous patches. However, I noticed that we don't have mips16 tests for MC.

[dsanders]

In D18179#379285, @vkalintiris wrote:

LGTM. I was going to ask for few test cases, as you've done with the previous patches. However, I noticed that we don't have mips16 tests for MC.

That's right (because MIPS16 lacks any IAS support at the moment) but it's not the reason for the lack of tests. These particular instructions are marked isCodeGenOnly so tablegen doesn't generate matching code for the assembly matcher in IAS. As a result, my change has no effect but I want to avoid leaving an unchecked immediate operand for whoever adds MIPS16 support to the MC layer in the future.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected 10-bit signed immediate");
   case Match_UImm16:
   case Match_UImm16_Relaxed:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected 16-bit unsigned immediate");
   case Match_UImm20_0:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected 20-bit unsigned immediate");
+  case Match_UImm26_0:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+                 "expected 26-bit unsigned immediate");
   }
 
   llvm_unreachable("Implement any new match types added!");
 }
 
 void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) {
   if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex)
     Warning(Loc, "used $at (currently $" + Twine(RegIndex) +

lib/Target/Mips/Mips16InstrInfo.td

class FEXT_CCRXI16_ins<string asmstr>:
   let isCodeGenOnly=1;
   let usesCustomInserter = 1;
 }
 
 // JAL and JALX instruction format
 //
 class FJAL16_ins<bits<1> _X, string asmstr,
                  InstrItinClass itin>:
-  FJAL16<_X, (outs), (ins simm20:$imm),
+  FJAL16<_X, (outs), (ins uimm26:$imm),
          !strconcat(asmstr, "\t$imm\n\tnop"),[],
          itin>  {
   let isCodeGenOnly=1;
   let Size=6;
 }
 
 class FJALB16_ins<bits<1> _X, string asmstr,
                  InstrItinClass itin>:
-  FJAL16<_X, (outs), (ins simm20:$imm),
+  FJAL16<_X, (outs), (ins uimm26:$imm),
          !strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
          itin>  {
   let isCodeGenOnly=1;
   let Size=6;
 }
 
 //
 // EXT-I instruction format

lib/Target/Mips/MipsInstrInfo.td

 //   The term 'superset' starts to break down here since the uimm5_plus* classes
 //   are not true supersets of uimm5 (but they are still subsets of uimm6).
 // * 'Relaxed' immediates are supersets of the corresponding unsigned immediate.
 //     uimm16 < uimm16_relaxed
 // * The codeGen pattern type is arbitrarily ordered.
 //     uimm5 < uimm5_64, and uimm5 < vsplat_uimm5
 //   This is entirely arbitrary. We need an ordering and what we pick is
 //   unimportant since only one is possible for a given mnemonic.
+def ConstantUImm26AsmOperandClass
+    : ConstantUImmAsmOperandClass<26, []>;
 def ConstantUImm20AsmOperandClass
-    : ConstantUImmAsmOperandClass<20, []>;
+    : ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>;
 def UImm16RelaxedAsmOperandClass
     : UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> {
   let Name = "UImm16_Relaxed";
   let PredicateMethod = "isAnyImm<16>";
   let DiagnosticType = "UImm16_Relaxed";
 }
 def UImm16AsmOperandClass
     : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;

 }
 
 def simm18_lsl3 : Operand<i32> {
   let EncoderMethod = "getSimm18Lsl3Encoding";
   let DecoderMethod = "DecodeSimm18Lsl3";
   let ParserMatchClass = MipsJumpTargetAsmOperand;
 }
 
-def simm20      : Operand<i32>;
 def simm32      : Operand<i32>;
 
 def simm16_64   : Operand<i64> {
   let DecoderMethod = "DecodeSimm16";
 }
 
 // Zero
 def uimmz       : Operand<i32> {
   let PrintMethod = "printUImm<0>";
   let ParserMatchClass = ConstantImmzAsmOperandClass;
 }
 
 // size operand of ins instruction
 def uimm_range_2_64 : Operand<i32> {
   let PrintMethod = "printUImm<6, 2>";
   let EncoderMethod = "getSizeInsEncoding";
   let DecoderMethod = "DecodeInsSize";
   let ParserMatchClass = ConstantUImm5_Range2_64AsmOperandClass;
 }
 
 // Unsigned Operands
-foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10, 20} in
+foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10, 20, 26} in
   def uimm # I : Operand<i32> {
     let PrintMethod = "printUImm<" # I # ">";
     let ParserMatchClass =
         !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
   }
 
 def uimm2_plus1 : Operand<i32> {
   let PrintMethod = "printUImm<2, 1>";