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Differential D18150

AMDGPU: Add frexp_mant intrinsic
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Authored by arsenm on Mar 14 2016, 10:14 AM.

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• tstellarAMD

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arsenm updated this revision to Diff 50610.Mar 14 2016, 10:14 AM
arsenm retitled this revision from to AMDGPU: Add frexp_mant intrinsic.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptMar 14 2016, 10:14 AM
• tstellarAMD accepted this revision.Mar 15 2016, 12:44 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Mar 15 2016, 12:44 PM
arsenm closed this revision.Mar 21 2016, 9:17 AM

r263948

Revision Contents

PathSize
include/
llvm/
IR/
4 lines
lib/
Target/
AMDGPU/
4 lines
test/
CodeGen/
AMDGPU/
64 lines

Diff 50610

include/llvm/IR/IntrinsicsAMDGPU.td

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def int_amdgcn_rsq_clamp : Intrinsic< def int_amdgcn_rsq_clamp : Intrinsic<
[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
def int_amdgcn_ldexp : Intrinsic< def int_amdgcn_ldexp : Intrinsic<
[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem] [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]
>; >;
def int_amdgcn_frexp_mant : Intrinsic<
[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
>;
def int_amdgcn_class : Intrinsic< def int_amdgcn_class : Intrinsic<
[llvm_i1_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem] [llvm_i1_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]
>; >;
def int_amdgcn_cubeid : GCCBuiltin<"__builtin_amdgcn_cubeid">, def int_amdgcn_cubeid : GCCBuiltin<"__builtin_amdgcn_cubeid">,
Intrinsic<[llvm_float_ty], Intrinsic<[llvm_float_ty],
[llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem] [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]
>; >;
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lib/Target/AMDGPU/SIInstructions.td

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defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>; defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>;
defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>; defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>;
defm V_FREXP_EXP_I32_F64 : VOP1Inst <vop1<0x3c,0x30>, "v_frexp_exp_i32_f64", defm V_FREXP_EXP_I32_F64 : VOP1Inst <vop1<0x3c,0x30>, "v_frexp_exp_i32_f64",
VOP_I32_F64 VOP_I32_F64
>; >;
let SchedRW = [WriteDoubleAdd] in { let SchedRW = [WriteDoubleAdd] in {
defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64", defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64",
VOP_F64_F64 VOP_F64_F64, int_amdgcn_frexp_mant
>; >;
defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64", defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64",
VOP_F64_F64 VOP_F64_F64
>; >;
} // End SchedRW = [WriteDoubleAdd] } // End SchedRW = [WriteDoubleAdd]
defm V_FREXP_EXP_I32_F32 : VOP1Inst <vop1<0x3f, 0x33>, "v_frexp_exp_i32_f32", defm V_FREXP_EXP_I32_F32 : VOP1Inst <vop1<0x3f, 0x33>, "v_frexp_exp_i32_f32",
VOP_I32_F32 VOP_I32_F32
>; >;
defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32", defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32",
VOP_F32_F32 VOP_F32_F32, int_amdgcn_frexp_mant
>; >;
let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in { let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NONE>; defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NONE>;
} }
let Uses = [M0, EXEC] in { let Uses = [M0, EXEC] in {
defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_I32_I32>; defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_I32_I32>;
defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_I32>; defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_I32>;
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test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll

  • This file was added.
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare float @llvm.fabs.f32(float) #0
declare double @llvm.fabs.f64(double) #0
declare float @llvm.amdgcn.frexp.mant.f32(float) #0
declare double @llvm.amdgcn.frexp.mant.f64(double) #0
; GCN-LABEL: {{^}}s_test_frexp_mant_f32:
; GCN: v_frexp_mant_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
define void @s_test_frexp_mant_f32(float addrspace(1)* %out, float %src) #1 {
%frexp.mant = call float @llvm.amdgcn.frexp.mant.f32(float %src)
store float %frexp.mant, float addrspace(1)* %out
ret void
}
; GCN-LABEL: {{^}}s_test_fabs_frexp_mant_f32:
; GCN: v_frexp_mant_f32_e64 {{v[0-9]+}}, |{{s[0-9]+}}|
define void @s_test_fabs_frexp_mant_f32(float addrspace(1)* %out, float %src) #1 {
%fabs.src = call float @llvm.fabs.f32(float %src)
%frexp.mant = call float @llvm.amdgcn.frexp.mant.f32(float %fabs.src)
store float %frexp.mant, float addrspace(1)* %out
ret void
}
; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_mant_f32:
; GCN: v_frexp_mant_f32_e64 {{v[0-9]+}}, -|{{s[0-9]+}}|
define void @s_test_fneg_fabs_frexp_mant_f32(float addrspace(1)* %out, float %src) #1 {
%fabs.src = call float @llvm.fabs.f32(float %src)
%fneg.fabs.src = fsub float -0.0, %fabs.src
%frexp.mant = call float @llvm.amdgcn.frexp.mant.f32(float %fneg.fabs.src)
store float %frexp.mant, float addrspace(1)* %out
ret void
}
; GCN-LABEL: {{^}}s_test_frexp_mant_f64:
; GCN: v_frexp_mant_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
define void @s_test_frexp_mant_f64(double addrspace(1)* %out, double %src) #1 {
%frexp.mant = call double @llvm.amdgcn.frexp.mant.f64(double %src)
store double %frexp.mant, double addrspace(1)* %out
ret void
}
; GCN-LABEL: {{^}}s_test_fabs_frexp_mant_f64:
; GCN: v_frexp_mant_f64_e64 {{v\[[0-9]+:[0-9]+\]}}, |{{s\[[0-9]+:[0-9]+\]}}|
define void @s_test_fabs_frexp_mant_f64(double addrspace(1)* %out, double %src) #1 {
%fabs.src = call double @llvm.fabs.f64(double %src)
%frexp.mant = call double @llvm.amdgcn.frexp.mant.f64(double %fabs.src)
store double %frexp.mant, double addrspace(1)* %out
ret void
}
; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_mant_f64:
; GCN: v_frexp_mant_f64_e64 {{v\[[0-9]+:[0-9]+\]}}, -|{{s\[[0-9]+:[0-9]+\]}}|
define void @s_test_fneg_fabs_frexp_mant_f64(double addrspace(1)* %out, double %src) #1 {
%fabs.src = call double @llvm.fabs.f64(double %src)
%fneg.fabs.src = fsub double -0.0, %fabs.src
%frexp.mant = call double @llvm.amdgcn.frexp.mant.f64(double %fneg.fabs.src)
store double %frexp.mant, double addrspace(1)* %out
ret void
}
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }