[mips] Eliminate instances of "potentially uninitialised local variable" warnings, NFC

[s.egerton]

Summary

This should eliminate all occurrences of this within LLVMMipsAsmParser.
This patch is in response to http://reviews.llvm.org/D17983. I was unable
to reproduce the warnings on my machine so please advise if this fixes the
warnings.

[dblaikie]

I'm still not sure cleaning up these warnings is worthwhile. If we aren't
going to get warning clean & keep the warning on/maintained (in which case
I'd really advocate for us to use Clang's version and/or implement the
necessary variant in Clang) what's the merit in rephrasing the cases that
aren't buggy (this appears to be such a case - correct me if I'm wrong?

[ariccio]

In D18087#373341, @dblaikie wrote:

I'm still not sure cleaning up these warnings is worthwhile. If we aren't
going to get warning clean & keep the warning on/maintained (in which case
I'd really advocate for us to use Clang's version and/or implement the
necessary variant in Clang) what's the merit in rephrasing the cases that
aren't buggy (this appears to be such a case - correct me if I'm wrong?

Generally, I agree, but the resulting code here is quite a bit clearer? Perhaps if not for the sake of cleaning up warnings, there are just fewer codepaths to maintain here?

[vkalintiris]

LGTM. Thanks for working on this.

[dsanders]

In D18087#373433, @ariccio wrote:

In D18087#373341, @dblaikie wrote:

I'm still not sure cleaning up these warnings is worthwhile. If we aren't
going to get warning clean & keep the warning on/maintained (in which case
I'd really advocate for us to use Clang's version and/or implement the
necessary variant in Clang) what's the merit in rephrasing the cases that
aren't buggy (this appears to be such a case - correct me if I'm wrong?

Generally, I agree, but the resulting code here is quite a bit clearer? Perhaps if not for the sake of cleaning up warnings, there are just fewer codepaths to maintain here?

This is my thinking too, the warning was a false-positive but the previous code was also unnecessarily complicated.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

else {
     emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, Instructions);
   }
   return false;
 }
 
 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
                                   SmallVectorImpl<MCInst> &Instructions,
                                   bool isLoad, bool isImmOpnd) {
-  unsigned ImmOffset, HiOffset, LoOffset;
-  const MCExpr *ExprOffset;
+  MCOperand HiOperand, LoOperand;
   unsigned TmpRegNum;
   // 1st operand is either the source or destination register.
   assert(Inst.getOperand(0).isReg() && "expected register operand kind");
   unsigned RegOpNum = Inst.getOperand(0).getReg();
   // 2nd operand is the base register.
   assert(Inst.getOperand(1).isReg() && "expected register operand kind");
   unsigned BaseRegNum = Inst.getOperand(1).getReg();
   // 3rd operand is either an immediate or expression.
   if (isImmOpnd) {
     assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
-    ImmOffset = Inst.getOperand(2).getImm();
-    LoOffset = ImmOffset & 0x0000ffff;
-    HiOffset = (ImmOffset & 0xffff0000) >> 16;
+    unsigned ImmOffset = Inst.getOperand(2).getImm();
+    unsigned LoOffset = ImmOffset & 0x0000ffff;
+    unsigned HiOffset = (ImmOffset & 0xffff0000) >> 16;
     // If msb of LoOffset is 1(negative number) we must increment HiOffset.
     if (LoOffset & 0x8000)
       HiOffset++;
-  } else
-    ExprOffset = Inst.getOperand(2).getExpr();
+    LoOperand = MCOperand::createImm(LoOffset);
+    HiOperand = MCOperand::createImm(HiOffset);
+  } else {
+    const MCExpr *ExprOffset = Inst.getOperand(2).getExpr();
+    LoOperand = MCOperand::createExpr(evaluateRelocExpr(ExprOffset, "lo"));
+    HiOperand = MCOperand::createExpr(evaluateRelocExpr(ExprOffset, "hi"));
+  }
   // These are some of the types of expansions we perform here:
   // 1) lw $8, sym        => lui $8, %hi(sym)
   //                         lw $8, %lo(sym)($8)
   // 2) lw $8, offset($9) => lui $8, %hi(offset)
   //                         add $8, $8, $9
   //                         lw $8, %lo(offset)($9)
   // 3) lw $8, offset($8) => lui $at, %hi(offset)
   //                         add $at, $at, $8
void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
   else {
     // At this point we need AT to perform the expansions and we exit if it is
     // not available.
     TmpRegNum = getATReg(IDLoc);
     if (!TmpRegNum)
       return;
   }
 
-  emitRX(Mips::LUi, TmpRegNum,
-         isImmOpnd ? MCOperand::createImm(HiOffset)
-                   : MCOperand::createExpr(evaluateRelocExpr(ExprOffset, "hi")),
-         IDLoc, Instructions);
+  emitRX(Mips::LUi, TmpRegNum, HiOperand, IDLoc, Instructions);
   // Add temp register to base.
   if (BaseRegNum != Mips::ZERO)
     emitRRR(Mips::ADDu, TmpRegNum, TmpRegNum, BaseRegNum, IDLoc, Instructions);
   // And finally, create original instruction with low part
   // of offset and new base.
-  emitRRX(Inst.getOpcode(), RegOpNum, TmpRegNum,
-          isImmOpnd
-              ? MCOperand::createImm(LoOffset)
-              : MCOperand::createExpr(evaluateRelocExpr(ExprOffset, "lo")),
-          IDLoc, Instructions);
+  emitRRX(Inst.getOpcode(), RegOpNum, TmpRegNum, LoOperand, IDLoc, Instructions);
 }
 
 bool
 MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
                                        SmallVectorImpl<MCInst> &Instructions) {
   unsigned OpNum = Inst.getNumOperands();
   unsigned Opcode = Inst.getOpcode();
   unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM;