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[AMDGPU] Fix VOPC instruction operand namings
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Authored by vpykhtin on Mar 8 2016, 11:09 AM.

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Reviewers

• tstellarAMD
arsenm

Commits

rGa7f480b4e998: [AMDGPU] Fix VOPC instruction operand namings
rL263242: [AMDGPU] Fix VOPC instruction operand namings

Summary

vsrc -> src

Diff Detail

Repository: rL LLVM

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vpykhtin updated this revision to Diff 50060.Mar 8 2016, 11:09 AM

vpykhtin retitled this revision from to [AMDGPU] Fix VOPC instruction operand namings.

vpykhtin updated this object.

vpykhtin added reviewers: arsenm, • tstellarAMD.

Herald added a subscriber: arsenm. · View Herald TranscriptMar 8 2016, 11:09 AM

vpykhtin added a subscriber: llvm-commits.Mar 9 2016, 9:31 AM

ping.

LGTM.

This revision is now accepted and ready to land.Mar 10 2016, 6:41 PM

Closed by commit rL263242: [AMDGPU] Fix VOPC instruction operand namings (authored by vpykhtin). · Explain WhyMar 11 2016, 6:58 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

llvm/

trunk/

lib/

Target/

AMDGPU/

SIInstrFormats.td

4 lines

test/

MC/

Disassembler/

AMDGPU/

vopc_vi.txt

25 lines

Diff 50426

llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td

Show First 20 Lines • Show All 439 Lines • ▼ Show 20 Lines	class VOP3be <bits<9> op> : Enc64 {
let Inst{60-59} = omod;		let Inst{60-59} = omod;
let Inst{61} = src0_modifiers{0};		let Inst{61} = src0_modifiers{0};
let Inst{62} = src1_modifiers{0};		let Inst{62} = src1_modifiers{0};
let Inst{63} = src2_modifiers{0};		let Inst{63} = src2_modifiers{0};
}		}

class VOPCe <bits<8> op> : Enc32 {		class VOPCe <bits<8> op> : Enc32 {
bits<9> src0;		bits<9> src0;
bits<8> vsrc1;		bits<8> src1;

let Inst{8-0} = src0;		let Inst{8-0} = src0;
let Inst{16-9} = vsrc1;		let Inst{16-9} = src1;
let Inst{24-17} = op;		let Inst{24-17} = op;
let Inst{31-25} = 0x3e;		let Inst{31-25} = 0x3e;
}		}

class VINTRPe <bits<2> op> : Enc32 {		class VINTRPe <bits<2> op> : Enc32 {
bits<8> vdst;		bits<8> vdst;
bits<8> vsrc;		bits<8> vsrc;
bits<2> attrchan;		bits<2> attrchan;
▲ Show 20 Lines • Show All 266 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Disassembler/AMDGPU/vopc_vi.txt

				# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s \| FileCheck %s -check-prefix=VI

				# VI: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x82,0x7c]
				0x02 0x08 0x82 0x7c

				# VI: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x82,0x7c]
				0x80 0x08 0x82 0x7c

				# VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
				0x02 0x09 0x82 0x7c

				# VI: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7c]
				0x02 0x09 0x80 0x7c

				# VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c]
				0x02 0x09 0x82 0x7c

				# VI: v_cmp_f_f64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7c]
				0x02 0x09 0xc0 0x7c

				# VI: v_cmp_f_i32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7d]
				0x02 0x09 0x80 0x7d

				# VI: v_cmp_f_i64_e32 vcc, v[2:3], v[4:5] ; encoding: [0x02,0x09,0xc0,0x7d]
				0x02 0x09 0xc0 0x7d