AVX512: Fix scalar mem operands in TD file.

[igorb]

Summary

AVX512: Fix scalar mem operands. Encoding tests was changed to force AV512 encoding ( after _Src.MemOp was changed to _Src.ScalarMemOp got AVX encoding)

[delena]

LGTM

llvm/trunk/lib/Target/X86/X86InstrAVX512.td

defm  rr_Int  : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
                       "vcmp${cc}"#_.Suffix,
                       "$src2, $src1", "$src1, $src2",
                       (OpNode (_.VT _.RC:$src1),
                               (_.VT _.RC:$src2),
                               imm:$cc)>, EVEX_4V;
   let mayLoad = 1 in
     defm  rm_Int  : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
                       (outs _.KRC:$dst),
-                      (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
+                      (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
                       "vcmp${cc}"#_.Suffix,
                       "$src2, $src1", "$src1, $src2",
                       (OpNode (_.VT _.RC:$src1),
                           (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
                           imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
 
   defm  rrb_Int  : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
                      (outs _.KRC:$dst),
                      (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
                      "vcmp${cc}"#_.Suffix,
                      "{sae}, $src2, $src1", "$src1, $src2, {sae}",
                      (OpNodeRnd (_.VT _.RC:$src1),
                                 (_.VT _.RC:$src2),
                                 imm:$cc,
                                 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
   // Accept explicit immediate argument form instead of comparison code.
   let isAsmParserOnly = 1, hasSideEffects = 0 in {
     defm  rri_alt  : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
                         (outs VK1:$dst),
                         (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
                         "vcmp"#_.Suffix,
                         "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
     defm  rmi_alt  : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
                         (outs _.KRC:$dst),
-                        (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
+                        (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
                         "vcmp"#_.Suffix,
                         "$cc, $src2, $src1", "$src1, $src2, $cc">,
                         EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
 
     defm  rrb_alt  : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
                        (outs _.KRC:$dst),
                        (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
                        "vcmp"#_.Suffix,
multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
   defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                            (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
                            "$src2, $src1", "$src1, $src2",
                            (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
                            (i32 FROUND_CURRENT)),
                            itins.rr, IsCommutable>;
 
   defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
-                         (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
+                         (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
                          "$src2, $src1", "$src1, $src2",
                          (VecNode (_.VT _.RC:$src1),
                           (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
                            (i32 FROUND_CURRENT)),
                          itins.rm, IsCommutable>;
   let isCodeGenOnly = 1, isCommutable = IsCommutable,
       Predicates = [HasAVX512] in {
   def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),

 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
                             X86VectorVTInfo _> {
   defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                   (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
                   "$src2, $src1", "$src1, $src2",
                   (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
   let mayLoad = 1 in {
     defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
-                    (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
+                    (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
                     "$src2, $src1", "$src1, $src2",
-                    (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
+                    (OpNode _.RC:$src1, 
+                            (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
+                            (i32 FROUND_CURRENT))>;
   }//let mayLoad = 1
 }
 
 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
   defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
              avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
                               EVEX_V512, EVEX_CD8<32, CD8VF>;
   defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
                                dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
                                                         dag RHS_r, dag RHS_m > {
   defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
           (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
           "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
 
   let mayLoad = 1 in
     defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
-            (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
+            (ins _.RC:$src2, _.ScalarMemOp:$src3), OpcodeStr,
             "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
 
   defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
          (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
          OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
                                        AVX512FMA3Base, EVEX_B, EVEX_RC;
 
   let isCodeGenOnly = 1 in {
multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
                             SDNode OpNodeRnd>{
 let Predicates = [HasAVX512] in {
   def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
               !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
               [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
   def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
                 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
                 []>, EVEX, EVEX_B;
-  def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
+  def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.ScalarMemOp:$src),
               !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
               [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
               EVEX;
 
   let isCodeGenOnly = 1,hasSideEffects = 0 in {
       def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
                 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
                [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
                          X86VectorVTInfo _Src, SDNode OpNode> {
   defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                          (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
                          "$src2, $src1", "$src1, $src2",
                          (_.VT (OpNode (_Src.VT _Src.RC:$src1),
                                        (_Src.VT _Src.RC:$src2)))>,
                          EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
   defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
-                         (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
+                         (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2), OpcodeStr,
                          "$src2, $src1", "$src1, $src2",
                          (_.VT (OpNode (_Src.VT _Src.RC:$src1),
                                   (_Src.VT (scalar_to_vector
                                             (_Src.ScalarLdFrag addr:$src2)))))>,
                          EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
 }
 
 // Scalar Coversion with SAE - suppress all exceptions
defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
                          (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
 
   defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
                          (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
                          (_.VT (OpNode (_Src.VT
                              (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
 
   defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
-                         (ins _Src.MemOp:$src), OpcodeStr,
+                         (ins _Src.ScalarMemOp:$src), OpcodeStr,
                          "${src}"##Broadcast, "${src}"##Broadcast,
                          (_.VT (OpNode (_Src.VT
                                   (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
                             ))>, EVEX, EVEX_B;
 }
 // Coversion with SAE - suppress all exceptions
 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
                          X86VectorVTInfo _Src, SDNode OpNodeRnd> {
multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
                             X86VectorVTInfo _> {
   let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
   defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                            (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
                            "$src2, $src1", "$src1, $src2",
                            (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
   let mayLoad = 1 in {
   defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
-                         (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
+                         (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
                          "$src2, $src1", "$src1, $src2",
                          (OpNode (_.VT _.RC:$src1),
                           (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
   }
 }
 }
 
 defm VRCP14SS   : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
 
   defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                             (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
                             "{sae}, $src2, $src1", "$src1, $src2, {sae}",
                             (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
                             (i32 FROUND_NO_EXC))>, EVEX_B;
 
   defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
-                         (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
+                         (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
                          "$src2, $src1", "$src1, $src2",
                          (OpNode (_.VT _.RC:$src1),
                           (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
                          (i32 FROUND_CURRENT))>;
 }
 
 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
   defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
 
   defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
                          (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
                          (OpNode (_.FloatVT
                              (bitconvert (_.LdFrag addr:$src))),
                           (i32 FROUND_CURRENT))>;
 
   defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
-                         (ins _.MemOp:$src), OpcodeStr,
+                         (ins _.ScalarMemOp:$src), OpcodeStr,
                          "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
                          (OpNode (_.FloatVT
                                   (X86VBroadcast (_.ScalarLdFrag addr:$src))),
                                  (i32 FROUND_CURRENT))>, EVEX_B;
 }
 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
                          SDNode OpNode> {
   defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
   defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                          (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
                          "$src2, $src1", "$src1, $src2",
                          (OpNodeRnd (_.VT _.RC:$src1),
                                     (_.VT _.RC:$src2),
                                     (i32 FROUND_CURRENT))>;
   let mayLoad = 1 in
     defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
-                         (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
+                         (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
                          "$src2, $src1", "$src1, $src2",
                          (OpNodeRnd (_.VT _.RC:$src1),
                                     (_.VT (scalar_to_vector
                                               (_.ScalarLdFrag addr:$src2))),
                                     (i32 FROUND_CURRENT))>;
 
   defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                          (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
   defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                          (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
                          "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
                          (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
                          (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
 
   let mayLoad = 1 in
   defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
-                         (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
+                         (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3), 
+                         OpcodeStr, 
                          "$src3, $src2, $src1", "$src1, $src2, $src3",
                          (_.VT (X86RndScales (_.VT _.RC:$src1),
                           (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
                           (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
   }
   let Predicates = [HasAVX512] in {
   def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
              (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),

llvm/trunk/test/MC/X86/avx512-encodings.s

 // CHECK: vaddss {rd-sae}, %xmm19, %xmm5, %xmm7
 // CHECK:  encoding: [0x62,0xb1,0x56,0x38,0x58,0xfb]
           vaddss {rd-sae}, %xmm19, %xmm5, %xmm7
 
 // CHECK: vaddss {rz-sae}, %xmm19, %xmm5, %xmm7
 // CHECK:  encoding: [0x62,0xb1,0x56,0x78,0x58,0xfb]
           vaddss {rz-sae}, %xmm19, %xmm5, %xmm7
 
-// CHECK: vaddss (%rcx), %xmm5, %xmm7
-// CHECK:  encoding: [0x62,0xf1,0x56,0x08,0x58,0x39]
-          vaddss (%rcx), %xmm5, %xmm7
-
-// CHECK: vaddss 291(%rax,%r14,8), %xmm5, %xmm7
-// CHECK:  encoding: [0x62,0xb1,0x56,0x08,0x58,0xbc,0xf0,0x23,0x01,0x00,0x00]
-          vaddss 291(%rax,%r14,8), %xmm5, %xmm7
-
-// CHECK: vaddss 508(%rdx), %xmm5, %xmm7
-// CHECK:  encoding: [0x62,0xf1,0x56,0x08,0x58,0x7a,0x7f]
-          vaddss 508(%rdx), %xmm5, %xmm7
-
-// CHECK: vaddss 512(%rdx), %xmm5, %xmm7
-// CHECK:  encoding: [0x62,0xf1,0x56,0x08,0x58,0xba,0x00,0x02,0x00,0x00]
-          vaddss 512(%rdx), %xmm5, %xmm7
-
-// CHECK: vaddss -512(%rdx), %xmm5, %xmm7
-// CHECK:  encoding: [0x62,0xf1,0x56,0x08,0x58,0x7a,0x80]
-          vaddss -512(%rdx), %xmm5, %xmm7
-
-// CHECK: vaddss -516(%rdx), %xmm5, %xmm7
-// CHECK:  encoding: [0x62,0xf1,0x56,0x08,0x58,0xba,0xfc,0xfd,0xff,0xff]
-          vaddss -516(%rdx), %xmm5, %xmm7
+// CHECK: vaddss (%rcx), %xmm25, %xmm7
+// CHECK:  encoding: [0x62,0xf1,0x36,0x00,0x58,0x39]
+          vaddss (%rcx), %xmm25, %xmm7
+
+// CHECK: vaddss 291(%rax,%r14,8), %xmm25, %xmm7
+// CHECK:  encoding: [0x62,0xb1,0x36,0x00,0x58,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vaddss 291(%rax,%r14,8), %xmm25, %xmm7
+
+// CHECK: vaddss 508(%rdx), %xmm25, %xmm7
+// CHECK:  encoding: [0x62,0xf1,0x36,0x00,0x58,0x7a,0x7f]
+          vaddss 508(%rdx), %xmm25, %xmm7
+
+// CHECK: vaddss 512(%rdx), %xmm25, %xmm7
+// CHECK:  encoding: [0x62,0xf1,0x36,0x00,0x58,0xba,0x00,0x02,0x00,0x00]
+          vaddss 512(%rdx), %xmm25, %xmm7
+
+// CHECK: vaddss -512(%rdx), %xmm25, %xmm7
+// CHECK:  encoding: [0x62,0xf1,0x36,0x00,0x58,0x7a,0x80]
+          vaddss -512(%rdx), %xmm25, %xmm7
+
+// CHECK: vaddss -516(%rdx), %xmm25, %xmm7
+// CHECK:  encoding: [0x62,0xf1,0x36,0x00,0x58,0xba,0xfc,0xfd,0xff,0xff]
+          vaddss -516(%rdx), %xmm25, %xmm7
 
 // CHECK: vdivpd {rn-sae}, %zmm11, %zmm6, %zmm18
 // CHECK:  encoding: [0x62,0xc1,0xcd,0x18,0x5e,0xd3]
           vdivpd {rn-sae}, %zmm11, %zmm6, %zmm18
 
 // CHECK: vdivpd {ru-sae}, %zmm11, %zmm6, %zmm18
 // CHECK:  encoding: [0x62,0xc1,0xcd,0x58,0x5e,0xd3]
           vdivpd {ru-sae}, %zmm11, %zmm6, %zmm18

 // CHECK: vmaxss %xmm6, %xmm4, %xmm8 {%k4} {z}
 // CHECK:  encoding: [0x62,0x71,0x5e,0x8c,0x5f,0xc6]
           vmaxss %xmm6, %xmm4, %xmm8 {%k4} {z}
 
 // CHECK: vmaxss {sae}, %xmm6, %xmm4, %xmm8
 // CHECK:  encoding: [0x62,0x71,0x5e,0x18,0x5f,0xc6]
           vmaxss {sae}, %xmm6, %xmm4, %xmm8
 
-// CHECK: vmaxss (%rcx), %xmm4, %xmm8
-// CHECK:  encoding: [0x62,0x71,0x5e,0x08,0x5f,0x01]
-          vmaxss (%rcx), %xmm4, %xmm8
-
-// CHECK: vmaxss 291(%rax,%r14,8), %xmm4, %xmm8
-// CHECK:  encoding: [0x62,0x31,0x5e,0x08,0x5f,0x84,0xf0,0x23,0x01,0x00,0x00]
-          vmaxss 291(%rax,%r14,8), %xmm4, %xmm8
-
-// CHECK: vmaxss 508(%rdx), %xmm4, %xmm8
-// CHECK:  encoding: [0x62,0x71,0x5e,0x08,0x5f,0x42,0x7f]
-          vmaxss 508(%rdx), %xmm4, %xmm8
-
-// CHECK: vmaxss 512(%rdx), %xmm4, %xmm8
-// CHECK:  encoding: [0x62,0x71,0x5e,0x08,0x5f,0x82,0x00,0x02,0x00,0x00]
-          vmaxss 512(%rdx), %xmm4, %xmm8
-
-// CHECK: vmaxss -512(%rdx), %xmm4, %xmm8
-// CHECK:  encoding: [0x62,0x71,0x5e,0x08,0x5f,0x42,0x80]
-          vmaxss -512(%rdx), %xmm4, %xmm8
-
-// CHECK: vmaxss -516(%rdx), %xmm4, %xmm8
-// CHECK:  encoding: [0x62,0x71,0x5e,0x08,0x5f,0x82,0xfc,0xfd,0xff,0xff]
-          vmaxss -516(%rdx), %xmm4, %xmm8
+// CHECK: vmaxss (%rcx), %xmm4, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x5e,0x08,0x5f,0x11]
+          vmaxss (%rcx), %xmm4, %xmm18
+
+// CHECK: vmaxss 291(%rax,%r14,8), %xmm4, %xmm18
+// CHECK:  encoding: [0x62,0xa1,0x5e,0x08,0x5f,0x94,0xf0,0x23,0x01,0x00,0x00]
+          vmaxss 291(%rax,%r14,8), %xmm4, %xmm18
+
+// CHECK: vmaxss 508(%rdx), %xmm4, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x5e,0x08,0x5f,0x52,0x7f]
+          vmaxss 508(%rdx), %xmm4, %xmm18
+
+// CHECK: vmaxss 512(%rdx), %xmm4, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x5e,0x08,0x5f,0x92,0x00,0x02,0x00,0x00]
+          vmaxss 512(%rdx), %xmm4, %xmm18
+
+// CHECK: vmaxss -512(%rdx), %xmm4, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x5e,0x08,0x5f,0x52,0x80]
+          vmaxss -512(%rdx), %xmm4, %xmm18
+
+// CHECK: vmaxss -516(%rdx), %xmm4, %xmm18
+// CHECK:  encoding: [0x62,0xe1,0x5e,0x08,0x5f,0x92,0xfc,0xfd,0xff,0xff]
+          vmaxss -516(%rdx), %xmm4, %xmm18
 
 // CHECK: vminpd {sae}, %zmm22, %zmm6, %zmm6
 // CHECK:  encoding: [0x62,0xb1,0xcd,0x18,0x5d,0xf6]
           vminpd {sae}, %zmm22, %zmm6, %zmm6
 
 // CHECK: vminps {sae}, %zmm7, %zmm3, %zmm3
 // CHECK:  encoding: [0x62,0xf1,0x64,0x18,0x5d,0xdf]
           vminps {sae}, %zmm7, %zmm3, %zmm3

 // CHECK: vmulsd {rd-sae}, %xmm18, %xmm4, %xmm13
 // CHECK:  encoding: [0x62,0x31,0xdf,0x38,0x59,0xea]
           vmulsd {rd-sae}, %xmm18, %xmm4, %xmm13
 
 // CHECK: vmulsd {rz-sae}, %xmm18, %xmm4, %xmm13
 // CHECK:  encoding: [0x62,0x31,0xdf,0x78,0x59,0xea]
           vmulsd {rz-sae}, %xmm18, %xmm4, %xmm13
 
-// CHECK: vmulsd (%rcx), %xmm4, %xmm13
-// CHECK:  encoding: [0x62,0x71,0xdf,0x08,0x59,0x29]
-          vmulsd (%rcx), %xmm4, %xmm13
-
-// CHECK: vmulsd 291(%rax,%r14,8), %xmm4, %xmm13
-// CHECK:  encoding: [0x62,0x31,0xdf,0x08,0x59,0xac,0xf0,0x23,0x01,0x00,0x00]
-          vmulsd 291(%rax,%r14,8), %xmm4, %xmm13
-
-// CHECK: vmulsd 1016(%rdx), %xmm4, %xmm13
-// CHECK:  encoding: [0x62,0x71,0xdf,0x08,0x59,0x6a,0x7f]
-          vmulsd 1016(%rdx), %xmm4, %xmm13
-
-// CHECK: vmulsd 1024(%rdx), %xmm4, %xmm13
-// CHECK:  encoding: [0x62,0x71,0xdf,0x08,0x59,0xaa,0x00,0x04,0x00,0x00]
-          vmulsd 1024(%rdx), %xmm4, %xmm13
-
-// CHECK: vmulsd -1024(%rdx), %xmm4, %xmm13
-// CHECK:  encoding: [0x62,0x71,0xdf,0x08,0x59,0x6a,0x80]
-          vmulsd -1024(%rdx), %xmm4, %xmm13
-
-// CHECK: vmulsd -1032(%rdx), %xmm4, %xmm13
-// CHECK:  encoding: [0x62,0x71,0xdf,0x08,0x59,0xaa,0xf8,0xfb,0xff,0xff]
-          vmulsd -1032(%rdx), %xmm4, %xmm13
+// CHECK: vmulsd (%rcx), %xmm4, %xmm23
+// CHECK:  encoding: [0x62,0xe1,0xdf,0x08,0x59,0x39]
+          vmulsd (%rcx), %xmm4, %xmm23
+
+// CHECK: vmulsd  291(%rax,%r14,8), %xmm4, %xmm23
+// CHECK: encoding: [0x62,0xa1,0xdf,0x08,0x59,0xbc,0xf0,0x23,0x01,0x00,0x00]
+          vmulsd  291(%rax,%r14,8), %xmm4, %xmm23
+
+// CHECK: vmulsd  1016(%rdx), %xmm4, %xmm23
+// CHECK: encoding: [0x62,0xe1,0xdf,0x08,0x59,0x7a,0x7f]
+          vmulsd  1016(%rdx), %xmm4, %xmm23
+
+// CHECK: vmulsd  1024(%rdx), %xmm4, %xmm23
+// CHECK: encoding: [0x62,0xe1,0xdf,0x08,0x59,0xba,0x00,0x04,0x00,0x00]
+          vmulsd  1024(%rdx), %xmm4, %xmm23
+
+// CHECK: vmulsd  -1024(%rdx), %xmm4, %xmm23
+// CHECK: encoding: [0x62,0xe1,0xdf,0x08,0x59,0x7a,0x80]
+          vmulsd  -1024(%rdx), %xmm4, %xmm23
+
+// CHECK: vmulsd  -1032(%rdx), %xmm4, %xmm23
+// CHECK: encoding: [0x62,0xe1,0xdf,0x08,0x59,0xba,0xf8,0xfb,0xff,0xff]
+          vmulsd  -1032(%rdx), %xmm4, %xmm23
 
 // CHECK: vmulss %xmm14, %xmm10, %xmm22
 // CHECK:  encoding: [0x62,0xc1,0x2e,0x08,0x59,0xf6]
           vmulss %xmm14, %xmm10, %xmm22
 
 // CHECK: vmulss %xmm14, %xmm10, %xmm22 {%k4}
 // CHECK:  encoding: [0x62,0xc1,0x2e,0x0c,0x59,0xf6]
           vmulss %xmm14, %xmm10, %xmm22 {%k4}