[SystemZ] Implement conditional returns.

[• koriakin]

Summary

Return is now considered a predicable instruction, and is converted
to a newly-added CondReturn (which maps to BCR to %r14) instruction by
the if conversion pass.

Also, fused compare-and-branch transform knows about conditional
returns, emitting the proper fused instructions for them.

This transform triggers on a *lot* of tests, hence the huge diffstat.
The changes are mostly jX to br %r14 -> bXr %r14.

[uweigand]

Your code changes look good in general. However, I agree that some of resulting transformations are less than optimal.

The if conversion happens before fused compares and BRCT are generated, thus winning over them. Could be OK for the fused compares, I suppose, but BRCT should be better than cond return. I suppose BRCT generation could be changed to cover that case, thoiugh. I've added junk instructions before return in the CIJ* and BRCT testcases to make sure they are still emitted.

For the fused compares, I think we should be able to get the best of both worlds by first generating the conditional return, and then fusing *that* with a compare into one of the C(G)RB or C(G)IB instructions (which LLVM currently doesn't use at all).

For BRCT, I suspect the problem is a special case of the strange loop transformation you mention later. If the backwards branch of the loop weren't modified by IfConversion, then the BRCT should still be detected.

Now as to that loop scenario, if I understand it correctly, it seems IfConversion recognizes the backwards branch of a loop at the very end of the function as an instance of the (inverted) ICSimple pattern. This seems questionable. I'm wondering whether this can be fixed in common code somehow (but I'm not sure if there's loop structure information available at this point in the process).

Failing that, I guess the backend's isProfitableToDupForIfCvt callback might try to detect that scenario via a low BranchProbability parameter being passed in (assuming that common code assigns a high probability to the backwards branch of a loop by default).

[• koriakin]

New version. Fused compare-and-branch instructions are emitted for conditional returns now, and the loop problem of the previous version is avoided based on branch probabilities. I'm now somewhat convinced that's the right way to do it (as opposed to looking at the loop structure) - for a loop with low loop probability (high return probability), like the compare-and-swap retries in atomicrmw-minmax-0[34].ll tests, the transform is actually still a win.

[uweigand]

LGTM, thanks! I'll check it in shortly ...

llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp

 void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   SystemZMCInstLower Lower(MF->getContext(), *this);
   MCInst LoweredMI;
   switch (MI->getOpcode()) {
   case SystemZ::Return:
     LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D);
     break;
 
+  case SystemZ::CondReturn:
+    LoweredMI = MCInstBuilder(SystemZ::BCR)
+      .addImm(MI->getOperand(0).getImm())
+      .addImm(MI->getOperand(1).getImm())
+      .addReg(SystemZ::R14D);
+    break;
+
+  case SystemZ::CRBReturn:
+    LoweredMI = MCInstBuilder(SystemZ::CRB)
+      .addReg(MI->getOperand(0).getReg())
+      .addReg(MI->getOperand(1).getReg())
+      .addImm(MI->getOperand(2).getImm())
+      .addReg(SystemZ::R14D)
+      .addImm(0);
+    break;
+
+  case SystemZ::CGRBReturn:
+    LoweredMI = MCInstBuilder(SystemZ::CGRB)
+      .addReg(MI->getOperand(0).getReg())
+      .addReg(MI->getOperand(1).getReg())
+      .addImm(MI->getOperand(2).getImm())
+      .addReg(SystemZ::R14D)
+      .addImm(0);
+    break;
+
+  case SystemZ::CIBReturn:
+    LoweredMI = MCInstBuilder(SystemZ::CIB)
+      .addReg(MI->getOperand(0).getReg())
+      .addImm(MI->getOperand(1).getImm())
+      .addImm(MI->getOperand(2).getImm())
+      .addReg(SystemZ::R14D)
+      .addImm(0);
+    break;
+
+  case SystemZ::CGIBReturn:
+    LoweredMI = MCInstBuilder(SystemZ::CGIB)
+      .addReg(MI->getOperand(0).getReg())
+      .addImm(MI->getOperand(1).getImm())
+      .addImm(MI->getOperand(2).getImm())
+      .addReg(SystemZ::R14D)
+      .addImm(0);
+    break;
+
+  case SystemZ::CLRBReturn:
+    LoweredMI = MCInstBuilder(SystemZ::CLRB)
+      .addReg(MI->getOperand(0).getReg())
+      .addReg(MI->getOperand(1).getReg())
+      .addImm(MI->getOperand(2).getImm())
+      .addReg(SystemZ::R14D)
+      .addImm(0);
+    break;
+
+  case SystemZ::CLGRBReturn:
+    LoweredMI = MCInstBuilder(SystemZ::CLGRB)
+      .addReg(MI->getOperand(0).getReg())
+      .addReg(MI->getOperand(1).getReg())
+      .addImm(MI->getOperand(2).getImm())
+      .addReg(SystemZ::R14D)
+      .addImm(0);
+    break;
+
+  case SystemZ::CLIBReturn:
+    LoweredMI = MCInstBuilder(SystemZ::CLIB)
+      .addReg(MI->getOperand(0).getReg())
+      .addImm(MI->getOperand(1).getImm())
+      .addImm(MI->getOperand(2).getImm())
+      .addReg(SystemZ::R14D)
+      .addImm(0);
+    break;
+
+  case SystemZ::CLGIBReturn:
+    LoweredMI = MCInstBuilder(SystemZ::CLGIB)
+      .addReg(MI->getOperand(0).getReg())
+      .addImm(MI->getOperand(1).getImm())
+      .addImm(MI->getOperand(2).getImm())
+      .addReg(SystemZ::R14D)
+      .addImm(0);
+    break;
+
   case SystemZ::CallBRASL:
     LoweredMI = MCInstBuilder(SystemZ::BRASL)
       .addReg(SystemZ::R14D)
       .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
     break;
 
   case SystemZ::CallBASR:
     LoweredMI = MCInstBuilder(SystemZ::BASR)

llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp

optimizeCompareZero(MachineInstr *Compare,
   return false;
 }
 
 // Try to fuse comparison instruction Compare into a later branch.
 // Return true on success and if Compare is therefore redundant.
 bool SystemZElimCompare::
 fuseCompareAndBranch(MachineInstr *Compare,
                      SmallVectorImpl<MachineInstr *> &CCUsers) {
-  // See whether we have a comparison that can be fused.
-  unsigned FusedOpcode = TII->getCompareAndBranch(Compare->getOpcode(),
-                                                  Compare);
-  if (!FusedOpcode)
-    return false;
-
   // See whether we have a single branch with which to fuse.
   if (CCUsers.size() != 1)
     return false;
   MachineInstr *Branch = CCUsers[0];
-  if (Branch->getOpcode() != SystemZ::BRC)
+  SystemZII::CompareAndBranchType Type;
+  switch (Branch->getOpcode()) {
+  case SystemZ::BRC:
+    Type = SystemZII::CompareAndBranch;
+    break;
+  case SystemZ::CondReturn:
+    Type = SystemZII::CompareAndReturn;
+    break;
+  default:
+    return false;
+  }
+
+  // See whether we have a comparison that can be fused.
+  unsigned FusedOpcode = TII->getCompareAndBranch(Compare->getOpcode(),
+                                                  Type, Compare);
+  if (!FusedOpcode)
     return false;
 
   // Make sure that the operands are available at the branch.
   unsigned SrcReg = Compare->getOperand(0).getReg();
   unsigned SrcReg2 = (Compare->getOperand(1).isReg() ?
                       Compare->getOperand(1).getReg() : 0);
   MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
   for (++MBBI; MBBI != MBBE; ++MBBI)
     if (MBBI->modifiesRegister(SrcReg, TRI) ||
         (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
       return false;
 
-  // Read the branch mask and target.
+  // Read the branch mask and target (if applicable).
   MachineOperand CCMask(MBBI->getOperand(1));
-  MachineOperand Target(MBBI->getOperand(2));
   assert((CCMask.getImm() & ~SystemZ::CCMASK_ICMP) == 0 &&
          "Invalid condition-code mask for integer comparison");
+  // This is only valid for CompareAndBranch.
+  MachineOperand Target(MBBI->getOperand(
+    Type == SystemZII::CompareAndBranch ? 2 : 0));
 
   // Clear out all current operands.
   int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
-  assert(CCUse >= 0 && "BRC must use CC");
+  assert(CCUse >= 0 && "BRC/BCR must use CC");
   Branch->RemoveOperand(CCUse);
+  if (Type == SystemZII::CompareAndBranch)
     Branch->RemoveOperand(2);
   Branch->RemoveOperand(1);
   Branch->RemoveOperand(0);
 
   // Rebuild Branch as a fused compare and branch.
   Branch->setDesc(TII->get(FusedOpcode));
-  MachineInstrBuilder(*Branch->getParent()->getParent(), Branch)
-    .addOperand(Compare->getOperand(0))
+  MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
+  MIB.addOperand(Compare->getOperand(0))
      .addOperand(Compare->getOperand(1))
-    .addOperand(CCMask)
-    .addOperand(Target)
+     .addOperand(CCMask);
+
+  if (Type == SystemZII::CompareAndBranch) {
+    // Only conditional branches define CC, as they may be converted back
+    // to a non-fused branch because of a long displacement.  Conditional
+    // returns don't have that problem.
+    MIB.addOperand(Target)
        .addReg(SystemZ::CC, RegState::ImplicitDefine);
+  }
 
   // Clear any intervening kills of SrcReg and SrcReg2.
   MBBI = Compare;
   for (++MBBI; MBBI != MBBE; ++MBBI) {
     MBBI->clearRegisterKills(SrcReg, TRI);
     if (SrcReg2)
       MBBI->clearRegisterKills(SrcReg2, TRI);
   }

llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h

struct Branch {
 
   // The target of the branch.
   const MachineOperand *Target;
 
   Branch(BranchType type, unsigned ccValid, unsigned ccMask,
          const MachineOperand *target)
     : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
 };
+// Kinds of branch in compare-and-branch instructions.  Together with type
+// of the converted compare, this identifies the compare-and-branch
+// instruction.
+enum CompareAndBranchType {
+  // Relative branch - CRJ etc.
+  CompareAndBranch,
+
+  // Indirect branch, used for return - CRBReturn etc.
+  CompareAndReturn
+};
 } // end namespace SystemZII
 
 class SystemZSubtarget;
 class SystemZInstrInfo : public SystemZGenInstrInfo {
   const SystemZRegisterInfo RI;
   SystemZSubtarget &STI;
 
   void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
public:
   bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
                            unsigned ExtraPredCycles,
                            BranchProbability Probability) const override;
   bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
                            unsigned NumCyclesT, unsigned ExtraPredCyclesT,
                            MachineBasicBlock &FMBB,
                            unsigned NumCyclesF, unsigned ExtraPredCyclesF,
                            BranchProbability Probability) const override;
+  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
+                            BranchProbability Probability) const override;
   bool PredicateInstruction(MachineInstr &MI,
                             ArrayRef<MachineOperand> Pred) const override;
   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                    DebugLoc DL, unsigned DestReg, unsigned SrcReg,
                    bool KillSrc) const override;
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
                            unsigned SrcReg, bool isKill, int FrameIndex,
public:
   // significant.  Set Start and End to the I3 and I4 operands if so.
   bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
                    unsigned &Start, unsigned &End) const;
 
   // If Opcode is a COMPARE opcode for which an associated COMPARE AND
   // BRANCH exists, return the opcode for the latter, otherwise return 0.
   // MI, if nonnull, is the compare instruction.
   unsigned getCompareAndBranch(unsigned Opcode,
+                               SystemZII::CompareAndBranchType Type,
                                const MachineInstr *MI = nullptr) const;
 
   // Emit code before MBBI in MI to move immediate value Value into
   // physical register Reg.
   void loadImmediate(MachineBasicBlock &MBB,
                      MachineBasicBlock::iterator MBBI,
                      unsigned Reg, uint64_t Value) const;
 };
 } // end namespace llvm
 
 #endif

llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp

static unsigned getConditionalMove(unsigned Opcode) {
   case SystemZ::LR:  return SystemZ::LOCR;
   case SystemZ::LGR: return SystemZ::LOCGR;
   default:           return 0;
   }
 }
 
 bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
   unsigned Opcode = MI.getOpcode();
-  return STI.hasLoadStoreOnCond() && getConditionalMove(Opcode);
+  if (STI.hasLoadStoreOnCond() && getConditionalMove(Opcode))
+    return true;
+  if (Opcode == SystemZ::Return)
+    return true;
+  return false;
 }
 
 bool SystemZInstrInfo::
 isProfitableToIfCvt(MachineBasicBlock &MBB,
                     unsigned NumCycles, unsigned ExtraPredCycles,
                     BranchProbability Probability) const {
+  // Avoid using conditional returns at the end of a loop (since then
+  // we'd need to emit an unconditional branch to the beginning anyway,
+  // making the loop body longer).  This doesn't apply for low-probability
+  // loops (eg. compare-and-swap retry), so just decide based on branch
+  // probability instead of looping structure.
+  if (MBB.succ_empty() && Probability < BranchProbability(1, 8))
+    return false;
   // For now only convert single instructions.
   return NumCycles == 1;
 }
 
 bool SystemZInstrInfo::
 isProfitableToIfCvt(MachineBasicBlock &TMBB,
                     unsigned NumCyclesT, unsigned ExtraPredCyclesT,
                     MachineBasicBlock &FMBB,
                     unsigned NumCyclesF, unsigned ExtraPredCyclesF,
                     BranchProbability Probability) const {
   // For now avoid converting mutually-exclusive cases.
   return false;
 }
 
+bool SystemZInstrInfo::
+isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
+                          BranchProbability Probability) const {
+  // For now only duplicate single instructions.
+  return NumCycles == 1;
+}
+
 bool SystemZInstrInfo::PredicateInstruction(
     MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
   assert(Pred.size() == 2 && "Invalid condition");
   unsigned CCValid = Pred[0].getImm();
   unsigned CCMask = Pred[1].getImm();
   assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
   unsigned Opcode = MI.getOpcode();
   if (STI.hasLoadStoreOnCond()) {
     if (unsigned CondOpcode = getConditionalMove(Opcode)) {
       MI.setDesc(get(CondOpcode));
       MachineInstrBuilder(*MI.getParent()->getParent(), MI)
           .addImm(CCValid)
           .addImm(CCMask)
           .addReg(SystemZ::CC, RegState::Implicit);
       return true;
     }
   }
+  if (Opcode == SystemZ::Return) {
+    MI.setDesc(get(SystemZ::CondReturn));
+    MachineInstrBuilder(*MI.getParent()->getParent(), MI)
+      .addImm(CCValid).addImm(CCMask)
+      .addReg(SystemZ::CC, RegState::Implicit);
+    return true;
+  }
   return false;
 }
 
 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MBBI,
                                    DebugLoc DL, unsigned DestReg,
                                    unsigned SrcReg, bool KillSrc) const {
   // Split 128-bit GPR moves into two 64-bit moves.  This handles ADDR128 too.
if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
     End = 63 - (LSB + Length);
     return true;
   }
 
   return false;
 }
 
 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
+                                               SystemZII::CompareAndBranchType Type,
                                                const MachineInstr *MI) const {
   switch (Opcode) {
+  case SystemZ::CHI:
+  case SystemZ::CGHI:
+    if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
+      return 0;
+    break;
+  case SystemZ::CLFI:
+  case SystemZ::CLGFI:
+    if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
+      return 0;
+  }
+  switch (Type) {
+  case SystemZII::CompareAndBranch:
+    switch (Opcode) {
     case SystemZ::CR:
       return SystemZ::CRJ;
     case SystemZ::CGR:
       return SystemZ::CGRJ;
     case SystemZ::CHI:
-    return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
+      return SystemZ::CIJ;
     case SystemZ::CGHI:
-    return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
+      return SystemZ::CGIJ;
     case SystemZ::CLR:
       return SystemZ::CLRJ;
     case SystemZ::CLGR:
       return SystemZ::CLGRJ;
     case SystemZ::CLFI:
-    return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLIJ : 0;
+      return SystemZ::CLIJ;
+    case SystemZ::CLGFI:
+      return SystemZ::CLGIJ;
+    default:
+      return 0;
+    }
+  case SystemZII::CompareAndReturn:
+    switch (Opcode) {
+    case SystemZ::CR:
+      return SystemZ::CRBReturn;
+    case SystemZ::CGR:
+      return SystemZ::CGRBReturn;
+    case SystemZ::CHI:
+      return SystemZ::CIBReturn;
+    case SystemZ::CGHI:
+      return SystemZ::CGIBReturn;
+    case SystemZ::CLR:
+      return SystemZ::CLRBReturn;
+    case SystemZ::CLGR:
+      return SystemZ::CLGRBReturn;
+    case SystemZ::CLFI:
+      return SystemZ::CLIBReturn;
     case SystemZ::CLGFI:
-    return MI && isUInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CLGIJ : 0;
+      return SystemZ::CLGIBReturn;
+    default:
+      return 0;
+    }
   default:
     return 0;
   }
 }
 
 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator MBBI,
                                      unsigned Reg, uint64_t Value) const {

llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td

 //===----------------------------------------------------------------------===//
 // Control flow instructions
 //===----------------------------------------------------------------------===//
 
 // A return instruction (br %r14).
 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
   def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
 
+// A conditional return instruction (bcr <cond>, %r14).
+let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in
+  def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;
+
+// Fused compare and conditional returns.
+let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, Uses = [CC] in {
+  def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
+  def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
+  def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;
+  def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;
+  def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
+  def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
+  def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;
+  def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;
+}
+
 // Unconditional branches.  R1 is the condition-code mask (all 1s).
 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
   let isIndirectBranch = 1 in
     def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
                     "br\t$R2", [(brind ADDR64:$R2)]>;
 
   // An assembler extended mnemonic for BRC.
   def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",

 // JE and JLH when writing out the assembly though.
 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
   let isCodeGenOnly = 1, CCMaskFirst = 1 in {
     def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
                                          brtarget16:$I2), "j$R1\t$I2",
                      [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
     def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
                                            brtarget32:$I2), "jg$R1\t$I2", []>;
+    let isIndirectBranch = 1 in
+      def BCR : InstRR<0x07, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
+                       "b${R1}r\t$R2", []>;
   }
   def AsmBRC : InstRI<0xA74, (outs), (ins imm32zx4:$R1, brtarget16:$I2),
                       "brc\t$R1, $I2", []>;
   def AsmBRCL : InstRIL<0xC04, (outs), (ins imm32zx4:$R1, brtarget32:$I2),
                         "brcl\t$R1, $I2", []>;
+  let isIndirectBranch = 1 in {
     def AsmBC : InstRX<0x47, (outs), (ins imm32zx4:$R1, bdxaddr12only:$XBD2),
                        "bc\t$R1, $XBD2", []>;
     def AsmBCR : InstRR<0x07, (outs), (ins imm32zx4:$R1, GR64:$R2),
                         "bcr\t$R1, $R2", []>;
   }
+}
 
 def AsmNop  : InstAlias<"nop\t$XBD", (AsmBC 0, bdxaddr12only:$XBD), 0>;
 def AsmNopR : InstAlias<"nopr\t$R", (AsmBCR 0, GR64:$R), 0>;
 
 // Fused compare-and-branch instructions.  As for normal branches,
 // we handle these instructions internally in their raw CRJ-like form,
 // but use assembly macros like CRJE when writing them out.
 //
def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
                                              brtarget16:$RI4),
                         "clgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
     def LIJ  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
                                              brtarget16:$RI4),
                         "clij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
     def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
                                              brtarget16:$RI4),
                         "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
+    let isIndirectBranch = 1 in {
       def RB  : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
                                              bdaddr12only:$BD4),
                         "crb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
       def GRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
                                              bdaddr12only:$BD4),
                         "cgrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
       def IB  : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
                                              bdaddr12only:$BD4),
                         "cib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
       def GIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
                                              bdaddr12only:$BD4),
                         "cgib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
       def LRB  : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
                                               bdaddr12only:$BD4),
                          "clrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
       def LGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
                                               bdaddr12only:$BD4),
                          "clgrb"##pos1##"\t$R1, $R2, "##pos2##"$BD4", []>;
       def LIB  : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
                                               bdaddr12only:$BD4),
                          "clib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
       def LGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
                                               bdaddr12only:$BD4),
                          "clgib"##pos1##"\t$R1, $I2, "##pos2##"$BD4", []>;
     }
   }
+}
 let isCodeGenOnly = 1 in
   defm C : CompareBranches<cond4, "$M3", "">;
 defm AsmC : CompareBranches<imm32zx4, "", "$M3, ">;
 
 // Define AsmParser mnemonics for each general condition-code mask
 // (integer or floating-point)
 multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
   let isBranch = 1, isTerminator = 1, R1 = ccmask in {
def CLGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
                                               brtarget16:$RI4),
                          "clgrj"##name##"\t$R1, $R2, $RI4", []>;
     def CLIJ  : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
                                               brtarget16:$RI4),
                          "clij"##name##"\t$R1, $I2, $RI4", []>;
     def CLGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
                                               brtarget16:$RI4),
                          "clgij"##name##"\t$R1, $I2, $RI4", []>;
+    let isIndirectBranch = 1 in {
       def CRB  : InstRRS<0xECF6, (outs), (ins GR32:$R1, GR32:$R2,
                                               bdaddr12only:$BD4),
                          "crb"##name##"\t$R1, $R2, $BD4", []>;
       def CGRB : InstRRS<0xECE4, (outs), (ins GR64:$R1, GR64:$R2,
                                               bdaddr12only:$BD4),
                          "cgrb"##name##"\t$R1, $R2, $BD4", []>;
       def CIB  : InstRIS<0xECFE, (outs), (ins GR32:$R1, imm32sx8:$I2,
                                               bdaddr12only:$BD4),
                          "cib"##name##"\t$R1, $I2, $BD4", []>;
       def CGIB : InstRIS<0xECFC, (outs), (ins GR64:$R1, imm64sx8:$I2,
                                               bdaddr12only:$BD4),
                          "cgib"##name##"\t$R1, $I2, $BD4", []>;
       def CLRB  : InstRRS<0xECF7, (outs), (ins GR32:$R1, GR32:$R2,
                                               bdaddr12only:$BD4),
                           "clrb"##name##"\t$R1, $R2, $BD4", []>;
       def CLGRB : InstRRS<0xECE5, (outs), (ins GR64:$R1, GR64:$R2,
                                                bdaddr12only:$BD4),
                           "clgrb"##name##"\t$R1, $R2, $BD4", []>;
       def CLIB  : InstRIS<0xECFF, (outs), (ins GR32:$R1, imm32zx8:$I2,
                                                bdaddr12only:$BD4),
                           "clib"##name##"\t$R1, $I2, $BD4", []>;
       def CLGIB : InstRIS<0xECFD, (outs), (ins GR64:$R1, imm64zx8:$I2,
                                                bdaddr12only:$BD4),
                           "clgib"##name##"\t$R1, $I2, $BD4", []>;
     }
   }
+}
 multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
   : IntCondExtendedMnemonicA<ccmask, name1> {
   let isAsmParserOnly = 1 in
     defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
 }
 defm AsmJH   : IntCondExtendedMnemonic<2,  "h",  "nle">;
 defm AsmJL   : IntCondExtendedMnemonic<4,  "l",  "nhe">;
 defm AsmJLH  : IntCondExtendedMnemonic<6,  "lh", "ne">;

llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp

 
  if (getOptLevel() != CodeGenOpt::None)
     addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
 
   return false;
 }
 
 void SystemZPassConfig::addPreSched2() {
-  if (getOptLevel() != CodeGenOpt::None &&
-      getSystemZTargetMachine().getSubtargetImpl()->hasLoadStoreOnCond())
+  if (getOptLevel() != CodeGenOpt::None)
     addPass(&IfConverterID);
 }
 
 void SystemZPassConfig::addPreEmitPass() {
 
   // Do instruction shortening before compare elimination because some
   // vector instructions will be shortened into opcodes that compare
   // elimination recognizes.

llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll

 ; Test 32-bit atomic minimum and maximum.  Here we match the z10 versions,
 ; which can't use LOCR.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check signed minium.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
 ; CHECK: crjle %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jl [[LOOP]]
-; CHECK: br %r14
+; CHECK: ber %r14
+; CHECK: j [[LOOP]]
   %res = atomicrmw min i32 *%src, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check signed maximum.
 define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
 ; CHECK: crjhe %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jl [[LOOP]]
-; CHECK: br %r14
+; CHECK: ber %r14
+; CHECK: j [[LOOP]]
   %res = atomicrmw max i32 *%src, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check unsigned minimum.
 define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
 ; CHECK: clrjle %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jl [[LOOP]]
-; CHECK: br %r14
+; CHECK: ber %r14
+; CHECK: j [[LOOP]]
   %res = atomicrmw umin i32 *%src, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check unsigned maximum.
 define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f4:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
 ; CHECK: clrjhe %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jl [[LOOP]]
-; CHECK: br %r14
+; CHECK: ber %r14
+; CHECK: j [[LOOP]]
   %res = atomicrmw umax i32 *%src, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check the high end of the aligned CS range.
 define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f5:
 ; CHECK: l %r2, 4092(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %ptr = getelementptr i32, i32 *%src, i64 1023
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check the next word up, which requires CSY.
 define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f6:
 ; CHECK: ly %r2, 4096(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %ptr = getelementptr i32, i32 *%src, i64 1024
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check the high end of the aligned CSY range.
 define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f7:
 ; CHECK: ly %r2, 524284(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %ptr = getelementptr i32, i32 *%src, i64 131071
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check the next word up, which needs separate address logic.
 define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, 524288
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %ptr = getelementptr i32, i32 *%src, i64 131072
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check the high end of the negative aligned CSY range.
 define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f9:
 ; CHECK: ly %r2, -4(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %ptr = getelementptr i32, i32 *%src, i64 -1
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check the low end of the CSY range.
 define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f10:
 ; CHECK: ly %r2, -524288(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %ptr = getelementptr i32, i32 *%src, i64 -131072
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check the next word down, which needs separate address logic.
 define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK-LABEL: f11:
 ; CHECK: agfi %r3, -524292
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %ptr = getelementptr i32, i32 *%src, i64 -131073
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check that indexed addresses are not allowed.
 define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
 ; CHECK-LABEL: f12:
 ; CHECK: agr %r3, %r4
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
   %res = atomicrmw min i32 *%ptr, i32 %b seq_cst
   ret i32 %res
 }
 
 ; Check that constants are handled.
 define i32 @f13(i32 %dummy, i32 *%ptr) {
 ; CHECK-LABEL: f13:
 ; CHECK: lhi [[LIMIT:%r[0-9]+]], 42
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
 ; CHECK: crjle %r2, [[LIMIT]], [[KEEP:\..*]]
 ; CHECK: lhi [[NEW]], 42
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jl [[LOOP]]
-; CHECK: br %r14
+; CHECK: ber %r14
+; CHECK: j [[LOOP]]
   %res = atomicrmw min i32 *%ptr, i32 42 seq_cst
   ret i32 %res
 }

llvm/trunk/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll

 ; Test 64-bit atomic minimum and maximum.  Here we match the z10 versions,
 ; which can't use LOCGR.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check signed minium.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
 ; CHECK: cgrjle %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jl [[LOOP]]
-; CHECK: br %r14
+; CHECK: ber %r14
+; CHECK: j [[LOOP]]
   %res = atomicrmw min i64 *%src, i64 %b seq_cst
   ret i64 %res
 }
 
 ; Check signed maximum.
 define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
 ; CHECK: cgrjhe %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jl [[LOOP]]
-; CHECK: br %r14
+; CHECK: ber %r14
+; CHECK: j [[LOOP]]
   %res = atomicrmw max i64 *%src, i64 %b seq_cst
   ret i64 %res
 }
 
 ; Check unsigned minimum.
 define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f3:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
 ; CHECK: clgrjle %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jl [[LOOP]]
-; CHECK: br %r14
+; CHECK: ber %r14
+; CHECK: j [[LOOP]]
   %res = atomicrmw umin i64 *%src, i64 %b seq_cst
   ret i64 %res
 }
 
 ; Check unsigned maximum.
 define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f4:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
 ; CHECK: clgrjhe %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jl [[LOOP]]
-; CHECK: br %r14
+; CHECK: ber %r14
+; CHECK: j [[LOOP]]
   %res = atomicrmw umax i64 *%src, i64 %b seq_cst
   ret i64 %res
 }
 
 ; Check the high end of the aligned CSG range.
 define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f5:
 ; CHECK: lg %r2, 524280(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %ptr = getelementptr i64, i64 *%src, i64 65535
   %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
 
 ; Check the next doubleword up, which requires separate address logic.
 define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %ptr = getelementptr i64, i64 *%src, i64 65536
   %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
 
 ; Check the low end of the CSG range.
 define i64 @f7(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f7:
 ; CHECK: lg %r2, -524288(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %ptr = getelementptr i64, i64 *%src, i64 -65536
   %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
 
 ; Check the next doubleword down, which requires separate address logic.
 define i64 @f8(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524296
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %ptr = getelementptr i64, i64 *%src, i64 -65537
   %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
 
 ; Check that indexed addresses are not allowed.
 define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
 ; CHECK-LABEL: f9:
 ; CHECK: agr %r3, %r4
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
-; CHECK: br %r14
+; CHECK: ber %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i64 *
   %res = atomicrmw min i64 *%ptr, i64 %b seq_cst
   ret i64 %res
 }
 
 ; Check that constants are handled.
 define i64 @f10(i64 %dummy, i64 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: lghi [[LIMIT:%r[0-9]+]], 42
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
 ; CHECK: cgrjle %r2, [[LIMIT]], [[KEEP:\..*]]
 ; CHECK: lghi [[NEW]], 42
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jl [[LOOP]]
-; CHECK: br %r14
+; CHECK: ber %r14
+; CHECK: j [[LOOP]]
   %res = atomicrmw min i64 *%ptr, i64 42 seq_cst
   ret i64 %res
 }

llvm/trunk/test/CodeGen/SystemZ/branch-05.ll

 ; Test indirect jumps.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i32 @f1(i32 %x, i32 %y, i32 %op) {
 ; CHECK-LABEL: f1:
 ; CHECK: ahi %r4, -1
-; CHECK: clijh %r4, 5,
+; CHECK: clibh %r4, 5, 0(%r14)
 ; CHECK: llgfr [[OP64:%r[0-5]]], %r4
 ; CHECK: sllg [[INDEX:%r[1-5]]], [[OP64]], 3
 ; CHECK: larl [[BASE:%r[1-5]]]
 ; CHECK: lg [[TARGET:%r[1-5]]], 0([[BASE]],[[INDEX]])
 ; CHECK: br [[TARGET]]
 entry:
   switch i32 %op, label %exit [
     i32 1, label %b.add

llvm/trunk/test/CodeGen/SystemZ/cond-store-01.ll

 ; Test 8-bit conditional stores that are presented as selects.  The volatile
 ; tests require z10, which use a branch instead of a LOCR.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 declare void @foo(i8 *)
 
 ; Test the simple case, with the loaded value first.
 define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
 ; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %alt, i8 %orig
   store i8 %res, i8 *%ptr
   ret void
 }
 
 ; Test cases where the value is explicitly sign-extended to 32 bits, with the
 ; loaded value first.
 define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %ext = sext i8 %orig to i32
   %res = select i1 %cond, i32 %ext, i32 %alt
   %trunc = trunc i32 %res to i8
   store i8 %trunc, i8 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %ext = sext i8 %orig to i32
   %res = select i1 %cond, i32 %alt, i32 %ext
   %trunc = trunc i32 %res to i8
   store i8 %trunc, i8 *%ptr
   ret void
 }
 
 ; Test cases where the value is explicitly zero-extended to 32 bits, with the
 ; loaded value first.
 define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %ext = zext i8 %orig to i32
   %res = select i1 %cond, i32 %ext, i32 %alt
   %trunc = trunc i32 %res to i8
   store i8 %trunc, i8 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %ext = zext i8 %orig to i32
   %res = select i1 %cond, i32 %alt, i32 %ext
   %trunc = trunc i32 %res to i8
   store i8 %trunc, i8 *%ptr
   ret void
 }
 
 ; Test cases where the value is explicitly sign-extended to 64 bits, with the
 ; loaded value first.
 define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %ext = sext i8 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i8
   store i8 %trunc, i8 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %ext = sext i8 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i8
   store i8 %trunc, i8 *%ptr
   ret void
 }
 
 ; Test cases where the value is explicitly zero-extended to 64 bits, with the
 ; loaded value first.
 define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %ext = zext i8 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i8
   store i8 %trunc, i8 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %ext = zext i8 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i8
   store i8 %trunc, i8 *%ptr
   ret void
 }
 
 ; Check the high end of the STC range.
 define void @f11(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK-LABEL: f11:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stc %r3, 4095(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i8, i8 *%base, i64 4095
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
 }
 
 ; Check the next byte up, which should use STCY instead of STC.
 define void @f12(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK-LABEL: f12:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stcy %r3, 4096(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i8, i8 *%base, i64 4096
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
 }
 
 ; Check the high end of the STCY range.
 define void @f13(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK-LABEL: f13:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stcy %r3, 524287(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i8, i8 *%base, i64 524287
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
 }
 
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f14(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK-LABEL: f14:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, 524288
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i8, i8 *%base, i64 524288
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
 }
 
 ; Check the low end of the STCY range.
 define void @f15(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK-LABEL: f15:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stcy %r3, -524288(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i8, i8 *%base, i64 -524288
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
 }
 
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f16(i8 *%base, i8 %alt, i32 %limit) {
 ; CHECK-LABEL: f16:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, -524289
 ; CHECK: stc %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i8, i8 *%base, i64 -524289
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr
   ret void
 }
 
 ; Check that STCY allows an index.
 define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) {
 ; CHECK-LABEL: f17:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stcy %r4, 4096(%r3,%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i8 *
   %cond = icmp ult i32 %limit, 420
   %orig = load i8 , i8 *%ptr
   %res = select i1 %cond, i8 %orig, i8 %alt
   store i8 %res, i8 *%ptr

llvm/trunk/test/CodeGen/SystemZ/cond-store-02.ll

 ; Test 16-bit conditional stores that are presented as selects.  The volatile
 ; tests require z10, which use a branch instead of a LOCR.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 declare void @foo(i16 *)
 
 ; Test the simple case, with the loaded value first.
 define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
 ; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %alt, i16 %orig
   store i16 %res, i16 *%ptr
   ret void
 }
 
 ; Test cases where the value is explicitly sign-extended to 32 bits, with the
 ; loaded value first.
 define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %ext = sext i16 %orig to i32
   %res = select i1 %cond, i32 %ext, i32 %alt
   %trunc = trunc i32 %res to i16
   store i16 %trunc, i16 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %ext = sext i16 %orig to i32
   %res = select i1 %cond, i32 %alt, i32 %ext
   %trunc = trunc i32 %res to i16
   store i16 %trunc, i16 *%ptr
   ret void
 }
 
 ; Test cases where the value is explicitly zero-extended to 32 bits, with the
 ; loaded value first.
 define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %ext = zext i16 %orig to i32
   %res = select i1 %cond, i32 %ext, i32 %alt
   %trunc = trunc i32 %res to i16
   store i16 %trunc, i16 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %ext = zext i16 %orig to i32
   %res = select i1 %cond, i32 %alt, i32 %ext
   %trunc = trunc i32 %res to i16
   store i16 %trunc, i16 *%ptr
   ret void
 }
 
 ; Test cases where the value is explicitly sign-extended to 64 bits, with the
 ; loaded value first.
 define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %ext = sext i16 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i16
   store i16 %trunc, i16 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %ext = sext i16 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i16
   store i16 %trunc, i16 *%ptr
   ret void
 }
 
 ; Test cases where the value is explicitly zero-extended to 64 bits, with the
 ; loaded value first.
 define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %ext = zext i16 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i16
   store i16 %trunc, i16 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %ext = zext i16 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i16
   store i16 %trunc, i16 *%ptr
   ret void
 }
 
 ; Check the high end of the aligned STH range.
 define void @f11(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK-LABEL: f11:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sth %r3, 4094(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 2047
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
 }
 
 ; Check the next halfword up, which should use STHY instead of STH.
 define void @f12(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK-LABEL: f12:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sthy %r3, 4096(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 2048
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
 }
 
 ; Check the high end of the aligned STHY range.
 define void @f13(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK-LABEL: f13:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sthy %r3, 524286(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 262143
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
 }
 
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f14(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK-LABEL: f14:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, 524288
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 262144
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
 }
 
 ; Check the low end of the STHY range.
 define void @f15(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK-LABEL: f15:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sthy %r3, -524288(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 -262144
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
 }
 
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f16(i16 *%base, i16 %alt, i32 %limit) {
 ; CHECK-LABEL: f16:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, -524290
 ; CHECK: sth %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 -262145
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr
   ret void
 }
 
 ; Check that STHY allows an index.
 define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) {
 ; CHECK-LABEL: f17:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sthy %r4, 4096(%r3,%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i16 *
   %cond = icmp ult i32 %limit, 420
   %orig = load i16 , i16 *%ptr
   %res = select i1 %cond, i16 %orig, i16 %alt
   store i16 %res, i16 *%ptr

llvm/trunk/test/CodeGen/SystemZ/cond-store-03.ll

 ; Test 32-bit conditional stores that are presented as selects.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 declare void @foo(i32 *)
 
 ; Test the simple case, with the loaded value first.
 define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: st %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: st %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %alt, i32 %orig
   store i32 %res, i32 *%ptr
   ret void
 }
 
 ; Test cases where the value is explicitly sign-extended to 64 bits, with the
 ; loaded value first.
 define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: st %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %ext = sext i32 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i32
   store i32 %trunc, i32 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: st %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %ext = sext i32 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i32
   store i32 %trunc, i32 *%ptr
   ret void
 }
 
 ; Test cases where the value is explicitly zero-extended to 32 bits, with the
 ; loaded value first.
 define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: st %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %ext = zext i32 %orig to i64
   %res = select i1 %cond, i64 %ext, i64 %alt
   %trunc = trunc i64 %res to i32
   store i32 %trunc, i32 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: st %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %ext = zext i32 %orig to i64
   %res = select i1 %cond, i64 %alt, i64 %ext
   %trunc = trunc i64 %res to i32
   store i32 %trunc, i32 *%ptr
   ret void
 }
 
 ; Check the high end of the aligned ST range.
 define void @f7(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: st %r3, 4092(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 1023
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
 }
 
 ; Check the next word up, which should use STY instead of ST.
 define void @f8(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sty %r3, 4096(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 1024
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
 }
 
 ; Check the high end of the aligned STY range.
 define void @f9(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sty %r3, 524284(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 131071
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
 }
 
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f10:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, 524288
 ; CHECK: st %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 131072
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
 }
 
 ; Check the low end of the STY range.
 define void @f11(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f11:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sty %r3, -524288(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -131072
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
 }
 
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f12(i32 *%base, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f12:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, -524292
 ; CHECK: st %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -131073
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr
   ret void
 }
 
 ; Check that STY allows an index.
 define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) {
 ; CHECK-LABEL: f13:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: sty %r4, 4096(%r3,%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
   %cond = icmp ult i32 %limit, 420
   %orig = load i32 , i32 *%ptr
   %res = select i1 %cond, i32 %orig, i32 %alt
   store i32 %res, i32 *%ptr

llvm/trunk/test/CodeGen/SystemZ/cond-store-04.ll

 ; Test 64-bit conditional stores that are presented as selects.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 declare void @foo(i64 *)
 
 ; Test with the loaded value first.
 define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stg %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: stg %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %alt, i64 %orig
   store i64 %res, i64 *%ptr
   ret void
 }
 
 ; Check the high end of the aligned STG range.
 define void @f3(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stg %r3, 524280(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 65535
   %cond = icmp ult i32 %limit, 420
   %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
 }
 
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, 524288
 ; CHECK: stg %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 65536
   %cond = icmp ult i32 %limit, 420
   %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
 }
 
 ; Check the low end of the STG range.
 define void @f5(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stg %r3, -524288(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 -65536
   %cond = icmp ult i32 %limit, 420
   %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
 }
 
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 *%base, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, -524296
 ; CHECK: stg %r3, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 -65537
   %cond = icmp ult i32 %limit, 420
   %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr
   ret void
 }
 
 ; Check that STG allows an index.
 define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stg %r4, 524287(%r3,%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to i64 *
   %cond = icmp ult i32 %limit, 420
   %orig = load i64 , i64 *%ptr
   %res = select i1 %cond, i64 %orig, i64 %alt
   store i64 %res, i64 *%ptr

llvm/trunk/test/CodeGen/SystemZ/cond-store-05.ll

 ; Test f32 conditional stores that are presented as selects.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 declare void @foo(float *)
 
 ; Test with the loaded value first.
 define void @f1(float *%ptr, float %alt, i32 %limit) {
 ; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: ste %f0, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f2(float *%ptr, float %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: ste %f0, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load float , float *%ptr
   %res = select i1 %cond, float %alt, float %orig
   store float %res, float *%ptr
   ret void
 }
 
 ; Check the high end of the aligned STE range.
 define void @f3(float *%base, float %alt, i32 %limit) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: ste %f0, 4092(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr float, float *%base, i64 1023
   %cond = icmp ult i32 %limit, 420
   %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
 }
 
 ; Check the next word up, which should use STEY instead of STE.
 define void @f4(float *%base, float %alt, i32 %limit) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stey %f0, 4096(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr float, float *%base, i64 1024
   %cond = icmp ult i32 %limit, 420
   %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
 }
 
 ; Check the high end of the aligned STEY range.
 define void @f5(float *%base, float %alt, i32 %limit) {
 ; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stey %f0, 524284(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr float, float *%base, i64 131071
   %cond = icmp ult i32 %limit, 420
   %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
 }
 
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(float *%base, float %alt, i32 %limit) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, 524288
 ; CHECK: ste %f0, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr float, float *%base, i64 131072
   %cond = icmp ult i32 %limit, 420
   %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
 }
 
 ; Check the low end of the STEY range.
 define void @f7(float *%base, float %alt, i32 %limit) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stey %f0, -524288(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr float, float *%base, i64 -131072
   %cond = icmp ult i32 %limit, 420
   %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
 }
 
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(float *%base, float %alt, i32 %limit) {
 ; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, -524292
 ; CHECK: ste %f0, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr float, float *%base, i64 -131073
   %cond = icmp ult i32 %limit, 420
   %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr
   ret void
 }
 
 ; Check that STEY allows an index.
 define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) {
 ; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stey %f0, 4096(%r3,%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to float *
   %cond = icmp ult i32 %limit, 420
   %orig = load float , float *%ptr
   %res = select i1 %cond, float %orig, float %alt
   store float %res, float *%ptr

llvm/trunk/test/CodeGen/SystemZ/cond-store-06.ll

 ; Test f64 conditional stores that are presented as selects.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 declare void @foo(double *)
 
 ; Test with the loaded value first.
 define void @f1(double *%ptr, double %alt, i32 %limit) {
 ; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: std %f0, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
 }
 
 ; ...and with the loaded value second
 define void @f2(double *%ptr, double %alt, i32 %limit) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
-; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: bher %r14
 ; CHECK-NOT: %r2
 ; CHECK: std %f0, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %cond = icmp ult i32 %limit, 420
   %orig = load double , double *%ptr
   %res = select i1 %cond, double %alt, double %orig
   store double %res, double *%ptr
   ret void
 }
 
 ; Check the high end of the aligned STD range.
 define void @f3(double *%base, double %alt, i32 %limit) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: std %f0, 4088(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr double, double *%base, i64 511
   %cond = icmp ult i32 %limit, 420
   %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
 }
 
 ; Check the next doubleword up, which should use STDY instead of STD.
 define void @f4(double *%base, double %alt, i32 %limit) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stdy %f0, 4096(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr double, double *%base, i64 512
   %cond = icmp ult i32 %limit, 420
   %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
 }
 
 ; Check the high end of the aligned STDY range.
 define void @f5(double *%base, double %alt, i32 %limit) {
 ; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stdy %f0, 524280(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr double, double *%base, i64 65535
   %cond = icmp ult i32 %limit, 420
   %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
 }
 
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(double *%base, double %alt, i32 %limit) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, 524288
 ; CHECK: std %f0, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr double, double *%base, i64 65536
   %cond = icmp ult i32 %limit, 420
   %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
 }
 
 ; Check the low end of the STDY range.
 define void @f7(double *%base, double %alt, i32 %limit) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stdy %f0, -524288(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr double, double *%base, i64 -65536
   %cond = icmp ult i32 %limit, 420
   %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
 }
 
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(double *%base, double %alt, i32 %limit) {
 ; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: agfi %r2, -524296
 ; CHECK: std %f0, 0(%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %ptr = getelementptr double, double *%base, i64 -65537
   %cond = icmp ult i32 %limit, 420
   %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr
   ret void
 }
 
 ; Check that STDY allows an index.
 define void @f9(i64 %base, i64 %index, double %alt, i32 %limit) {
 ; CHECK-LABEL: f9:
 ; CHECK-NOT: %r2
-; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK: blr %r14
 ; CHECK-NOT: %r2
 ; CHECK: stdy %f0, 524287(%r3,%r2)
-; CHECK: [[LABEL]]:
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 524287
   %ptr = inttoptr i64 %add2 to double *
   %cond = icmp ult i32 %limit, 420
   %orig = load double , double *%ptr
   %res = select i1 %cond, double %orig, double %alt
   store double %res, double *%ptr

llvm/trunk/test/CodeGen/SystemZ/fp-cmp-01.ll

 ; Test 32-bit floating-point comparison.  The tests assume a z10 implementation
 ; of select, using conditional branches rather than LOCGR.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 declare float @foo()
 
 ; Check comparison with registers.
 define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) {
 ; CHECK-LABEL: f1:
 ; CHECK: cebr %f0, %f2
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check the low end of the CEB range.
 define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f2 = load float , float *%ptr
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check the high end of the aligned CEB range.
 define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: ceb %f0, 4092(%r4)
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %ptr = getelementptr float, float *%base, i64 1023
   %f2 = load float , float *%ptr
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) {
 ; CHECK-LABEL: f4:
 ; CHECK: aghi %r4, 4096
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %ptr = getelementptr float, float *%base, i64 1024
   %f2 = load float , float *%ptr
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check negative displacements, which also need separate address logic.
 define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) {
 ; CHECK-LABEL: f5:
 ; CHECK: aghi %r4, -4
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %ptr = getelementptr float, float *%base, i64 -1
   %f2 = load float , float *%ptr
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check that CEB allows indices.
 define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) {
 ; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r5, 2
 ; CHECK: ceb %f0, 400(%r1,%r4)
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %ptr1 = getelementptr float, float *%base, i64 %index
   %ptr2 = getelementptr float, float *%ptr1, i64 100
   %f2 = load float , float *%ptr2
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
; CHECK: br %r14
 
   ret float %sel10
 }
 
 ; Check comparison with zero.
 define i64 @f8(i64 %a, i64 %b, float %f) {
 ; CHECK-LABEL: f8:
 ; CHECK: ltebr %f0, %f0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %cond = fcmp oeq float %f, 0.0
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check the comparison can be reversed if that allows CEB to be used,
 ; first with oeq.
 define i64 @f9(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: je {{\.L.*}}
+; CHECK-NEXT: ber %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp oeq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; ...then one.
 define i64 @f10(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: jlh {{\.L.*}}
+; CHECK-NEXT: blhr %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp one float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; ...then olt.
 define i64 @f11(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp olt float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; ...then ole.
 define i64 @f12(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f12:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: jhe {{\.L.*}}
+; CHECK-NEXT: bher %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp ole float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; ...then oge.
 define i64 @f13(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f13:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: jle {{\.L.*}}
+; CHECK-NEXT: bler %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp oge float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; ...then ogt.
 define i64 @f14(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f14:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: jl {{\.L.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp ogt float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; ...then ueq.
 define i64 @f15(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f15:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: jnlh {{\.L.*}}
+; CHECK-NEXT: bnlhr %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp ueq float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; ...then une.
 define i64 @f16(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f16:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: jne {{\.L.*}}
+; CHECK-NEXT: bner %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp une float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; ...then ult.
 define i64 @f17(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f17:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: jnle {{\.L.*}}
+; CHECK-NEXT: bnler %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp ult float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; ...then ule.
 define i64 @f18(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f18:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: jnl {{\.L.*}}
+; CHECK-NEXT: bnlr %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp ule float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; ...then uge.
 define i64 @f19(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f19:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: jnh {{\.L.*}}
+; CHECK-NEXT: bnhr %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp uge float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; ...then ugt.
 define i64 @f20(i64 %a, i64 %b, float %f2, float *%ptr) {
 ; CHECK-LABEL: f20:
 ; CHECK: ceb %f0, 0(%r4)
-; CHECK-NEXT: jnhe {{\.L.*}}
+; CHECK-NEXT: bnher %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f1 = load float , float *%ptr
   %cond = fcmp ugt float %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }

llvm/trunk/test/CodeGen/SystemZ/fp-cmp-02.ll

 ; Test 64-bit floating-point comparison.  The tests assume a z10 implementation
 ; of select, using conditional branches rather than LOCGR.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 \
 ; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-SCALAR %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs\
 ; RUN:   | FileCheck -check-prefix=CHECK -check-prefix=CHECK-VECTOR %s
 
 declare double @foo()
 
 ; Check comparison with registers.
 define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) {
 ; CHECK-LABEL: f1:
 ; CHECK: cdbr %f0, %f2
-; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR-NEXT: ber %r14
 ; CHECK-SCALAR: lgr %r2, %r3
 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check the low end of the CDB range.
 define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cdb %f0, 0(%r4)
-; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR-NEXT: ber %r14
 ; CHECK-SCALAR: lgr %r2, %r3
 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
   %f2 = load double , double *%ptr
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check the high end of the aligned CDB range.
 define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: cdb %f0, 4088(%r4)
-; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR-NEXT: ber %r14
 ; CHECK-SCALAR: lgr %r2, %r3
 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
   %ptr = getelementptr double, double *%base, i64 511
   %f2 = load double , double *%ptr
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) {
 ; CHECK-LABEL: f4:
 ; CHECK: aghi %r4, 4096
 ; CHECK: cdb %f0, 0(%r4)
-; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR-NEXT: ber %r14
 ; CHECK-SCALAR: lgr %r2, %r3
 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
   %ptr = getelementptr double, double *%base, i64 512
   %f2 = load double , double *%ptr
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check negative displacements, which also need separate address logic.
 define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) {
 ; CHECK-LABEL: f5:
 ; CHECK: aghi %r4, -8
 ; CHECK: cdb %f0, 0(%r4)
-; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR-NEXT: ber %r14
 ; CHECK-SCALAR: lgr %r2, %r3
 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
   %ptr = getelementptr double, double *%base, i64 -1
   %f2 = load double , double *%ptr
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check that CDB allows indices.
 define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) {
 ; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r5, 3
 ; CHECK: cdb %f0, 800(%r1,%r4)
-; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR-NEXT: ber %r14
 ; CHECK-SCALAR: lgr %r2, %r3
 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
   %ptr1 = getelementptr double, double *%base, i64 %index
   %ptr2 = getelementptr double, double *%ptr1, i64 100
   %f2 = load double , double *%ptr2
   %cond = fcmp oeq double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
; CHECK: br %r14
 
   ret double %sel10
 }
 
 ; Check comparison with zero.
 define i64 @f8(i64 %a, i64 %b, double %f) {
 ; CHECK-LABEL: f8:
 ; CHECK-SCALAR: ltdbr %f0, %f0
-; CHECK-SCALAR-NEXT: je
+; CHECK-SCALAR-NEXT: ber %r14
 ; CHECK-SCALAR: lgr %r2, %r3
 ; CHECK-VECTOR: ltdbr %f0, %f0
 ; CHECK-VECTOR-NEXT: locgrne %r2, %r3
 ; CHECK: br %r14
   %cond = fcmp oeq double %f, 0.0
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check the comparison can be reversed if that allows CDB to be used,
 define i64 @f9(i64 %a, i64 %b, double %f2, double *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: cdb %f0, 0(%r4)
-; CHECK-SCALAR-NEXT: jl
+; CHECK-SCALAR-NEXT: blr %r14
 ; CHECK-SCALAR: lgr %r2, %r3
 ; CHECK-VECTOR-NEXT: locgrnl %r2, %r3
 ; CHECK: br %r14
   %f1 = load double , double *%ptr
   %cond = fcmp ogt double %f1, %f2
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }

llvm/trunk/test/CodeGen/SystemZ/fp-cmp-03.ll

 ; Test 128-bit floating-point comparison.  The tests assume a z10 implementation
 ; of select, using conditional branches rather than LOCGR.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; There is no memory form of 128-bit comparison.
 define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
 ; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r4)
 ; CHECK: ld %f3, 8(%r4)
 ; CHECK: cxbr %f1, %f0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f2x = fpext float %f2 to fp128
   %f1 = load fp128 , fp128 *%ptr
   %cond = fcmp oeq fp128 %f1, %f2x
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
 
 ; Check comparison with zero.
 define i64 @f2(i64 %a, i64 %b, fp128 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: ld %f0, 0(%r4)
 ; CHECK: ld %f2, 8(%r4)
 ; CHECK: ltxbr %f0, %f0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   %f = load fp128 , fp128 *%ptr
   %cond = fcmp oeq fp128 %f, 0xL00000000000000000000000000000000
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }

llvm/trunk/test/CodeGen/SystemZ/fp-cmp-04.ll

 ; Test that floating-point compares are omitted if CC already has the
 ; right value.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-integrated-as | FileCheck %s
 
 declare float @llvm.fabs.f32(float %f)
 
 ; Test addition followed by EQ, which can use the CC result of the addition.
 define float @f1(float %a, float %b, float *%dest) {
 ; CHECK-LABEL: f1:
 ; CHECK: aebr %f0, %f2
-; CHECK-NEXT: je .L{{.*}}
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %res = fadd float %a, %b
   %cmp = fcmp oeq float %res, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %b, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; ...and again with LT.
 define float @f2(float %a, float %b, float *%dest) {
 ; CHECK-LABEL: f2:
 ; CHECK: aebr %f0, %f2
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %res = fadd float %a, %b
   %cmp = fcmp olt float %res, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %b, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; ...and again with GT.
 define float @f3(float %a, float %b, float *%dest) {
 ; CHECK-LABEL: f3:
 ; CHECK: aebr %f0, %f2
-; CHECK-NEXT: jh .L{{.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %res = fadd float %a, %b
   %cmp = fcmp ogt float %res, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %b, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; ...and again with UEQ.
 define float @f4(float %a, float %b, float *%dest) {
 ; CHECK-LABEL: f4:
 ; CHECK: aebr %f0, %f2
-; CHECK-NEXT: jnlh .L{{.*}}
+; CHECK-NEXT: bnlhr %r14
 ; CHECK: br %r14
 entry:
   %res = fadd float %a, %b
   %cmp = fcmp ueq float %res, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %b, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; Subtraction also provides a zero-based CC value.
 define float @f5(float %a, float %b, float *%dest) {
 ; CHECK-LABEL: f5:
 ; CHECK: seb %f0, 0(%r2)
-; CHECK-NEXT: jnhe .L{{.*}}
+; CHECK-NEXT: bnher %r14
 ; CHECK: br %r14
 entry:
   %cur = load float , float *%dest
   %res = fsub float %a, %cur
   %cmp = fcmp ult float %res, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %b, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; Test the result of LOAD POSITIVE.
 define float @f6(float %dummy, float %a, float *%dest) {
 ; CHECK-LABEL: f6:
 ; CHECK: lpebr %f0, %f2
-; CHECK-NEXT: jh .L{{.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %res = call float @llvm.fabs.f32(float %a)
   %cmp = fcmp ogt float %res, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %res, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; Test the result of LOAD NEGATIVE.
 define float @f7(float %dummy, float %a, float *%dest) {
 ; CHECK-LABEL: f7:
 ; CHECK: lnebr %f0, %f2
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %abs = call float @llvm.fabs.f32(float %a)
   %res = fsub float -0.0, %abs
   %cmp = fcmp olt float %res, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %res, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; Test the result of LOAD COMPLEMENT.
 define float @f8(float %dummy, float %a, float *%dest) {
 ; CHECK-LABEL: f8:
 ; CHECK: lcebr %f0, %f2
-; CHECK-NEXT: jle .L{{.*}}
+; CHECK-NEXT: bler %r14
 ; CHECK: br %r14
 entry:
   %res = fsub float -0.0, %a
   %cmp = fcmp ole float %res, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %res, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; Multiplication (for example) does not modify CC.
 define float @f9(float %a, float %b, float *%dest) {
 ; CHECK-LABEL: f9:
 ; CHECK: meebr %f0, %f2
 ; CHECK-NEXT: ltebr %f0, %f0
-; CHECK-NEXT: jlh .L{{.*}}
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
 entry:
   %res = fmul float %a, %b
   %cmp = fcmp one float %res, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %b, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; Test a combination involving a CC-setting instruction followed by
 ; a non-CC-setting instruction.
 define float @f10(float %a, float %b, float %c, float *%dest) {
 ; CHECK-LABEL: f10:
 ; CHECK: aebr %f0, %f2
 ; CHECK-NEXT: debr %f0, %f4
 ; CHECK-NEXT: ltebr %f0, %f0
-; CHECK-NEXT: jne .L{{.*}}
+; CHECK-NEXT: bner %r14
 ; CHECK: br %r14
 entry:
   %add = fadd float %a, %b
   %res = fdiv float %add, %c
   %cmp = fcmp une float %res, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %b, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; Test a case where CC is set based on a different register from the
 ; compare input.
 define float @f11(float %a, float %b, float %c, float *%dest1, float *%dest2) {
 ; CHECK-LABEL: f11:
 ; CHECK: aebr %f0, %f2
 ; CHECK-NEXT: sebr %f4, %f0
 ; CHECK-NEXT: ste %f4, 0(%r2)
 ; CHECK-NEXT: ltebr %f0, %f0
-; CHECK-NEXT: je .L{{.*}}
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %add = fadd float %a, %b
   %sub = fsub float %c, %add
   store float %sub, float *%dest1
   %cmp = fcmp oeq float %add, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %sub, float *%dest2
   br label %exit
 
 exit:
   ret float %add
 }
 
 ; Test that LER gets converted to LTEBR where useful.
 define float @f12(float %dummy, float %val, float *%dest) {
 ; CHECK-LABEL: f12:
 ; CHECK: ltebr %f0, %f2
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %f0
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   call void asm sideeffect "blah $0", "{f0}"(float %val)
   %cmp = fcmp olt float %val, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %val, float *%dest
   br label %exit
 
 exit:
   ret float %val
 }
 
 ; Test that LDR gets converted to LTDBR where useful.
 define double @f13(double %dummy, double %val, double *%dest) {
 ; CHECK-LABEL: f13:
 ; CHECK: ltdbr %f0, %f2
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %f0
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   call void asm sideeffect "blah $0", "{f0}"(double %val)
   %cmp = fcmp olt double %val, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store double %val, double *%dest
   br label %exit
 
 exit:
   ret double %val
 }
 
 ; Test that LXR gets converted to LTXBR where useful.
 define void @f14(fp128 *%ptr1, fp128 *%ptr2) {
 ; CHECK-LABEL: f14:
 ; CHECK: ltxbr
 ; CHECK-NEXT: dxbr
 ; CHECK-NEXT: std
 ; CHECK-NEXT: std
 ; CHECK-NEXT: mxbr
 ; CHECK-NEXT: std
 ; CHECK-NEXT: std
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %val1 = load fp128 , fp128 *%ptr1
   %val2 = load fp128 , fp128 *%ptr2
   %div = fdiv fp128 %val1, %val2
   store fp128 %div, fp128 *%ptr1
   %mul = fmul fp128 %val1, %val2
   store fp128 %mul, fp128 *%ptr2

 ; Test a case where it is the source rather than destination of LER that
 ; we need.
 define float @f15(float %val, float %dummy, float *%dest) {
 ; CHECK-LABEL: f15:
 ; CHECK: ltebr %f2, %f0
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %f2
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   call void asm sideeffect "blah $0", "{f2}"(float %val)
   %cmp = fcmp olt float %val, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %val, float *%dest
   br label %exit
 
 exit:
   ret float %val
 }
 
 ; Test a case where it is the source rather than destination of LDR that
 ; we need.
 define double @f16(double %val, double %dummy, double *%dest) {
 ; CHECK-LABEL: f16:
 ; CHECK: ltdbr %f2, %f0
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %f2
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   call void asm sideeffect "blah $0", "{f2}"(double %val)
   %cmp = fcmp olt double %val, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store double %val, double *%dest
   br label %exit
 
 exit:
   ret double %val
 }
 
 ; Repeat f2 with a comparison against -0.
 define float @f17(float %a, float %b, float *%dest) {
 ; CHECK-LABEL: f17:
 ; CHECK: aebr %f0, %f2
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %res = fadd float %a, %b
   %cmp = fcmp olt float %res, -0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %b, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; Test another form of f7 in which the condition is based on the unnegated
 ; result.  This is what InstCombine would produce.
 define float @f18(float %dummy, float %a, float *%dest) {
 ; CHECK-LABEL: f18:
 ; CHECK: lnebr %f0, %f2
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %abs = call float @llvm.fabs.f32(float %a)
   %res = fsub float -0.0, %abs
   %cmp = fcmp ogt float %abs, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %res, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }
 
 ; Similarly for f8.
 define float @f19(float %dummy, float %a, float *%dest) {
 ; CHECK-LABEL: f19:
 ; CHECK: lcebr %f0, %f2
-; CHECK-NEXT: jle .L{{.*}}
+; CHECK-NEXT: bler %r14
 ; CHECK: br %r14
 entry:
   %res = fsub float -0.0, %a
   %cmp = fcmp oge float %a, 0.0
   br i1 %cmp, label %exit, label %store
 
 store:
   store float %res, float *%dest
   br label %exit
 
 exit:
   ret float %res
 }

llvm/trunk/test/CodeGen/SystemZ/fp-cmp-05.ll

 ; Test that floating-point instructions that set cc are used to
 ; eliminate compares for load complement, load negative and load
 ; positive.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 
 ; Load complement (sign-bit flipped).
 ; Test f32
 define float @f1(float %a, float %b, float %f) {
 ; CHECK-LABEL: f1:
 ; CHECK: lcebr
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
   %neg = fsub float -0.0, %f
   %cond = fcmp oeq float %neg, 0.0
   %res = select i1 %cond, float %a, float %b
   ret float %res
 }
 
 ; Test f64
 define double @f2(double %a, double %b, double %f) {
 ; CHECK-LABEL: f2:
 ; CHECK: lcdbr
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
   %neg = fsub double -0.0, %f
   %cond = fcmp oeq double %neg, 0.0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Negation of floating-point absolute.
 ; Test f32
 declare float @llvm.fabs.f32(float %f)
 define float @f3(float %a, float %b, float %f) {
 ; CHECK-LABEL: f3:
 ; CHECK: lnebr
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
   %abs = call float @llvm.fabs.f32(float %f)
   %neg = fsub float -0.0, %abs
   %cond = fcmp oeq float %neg, 0.0
   %res = select i1 %cond, float %a, float %b
   ret float %res
 }
 
 ; Test f64
 declare double @llvm.fabs.f64(double %f)
 define double @f4(double %a, double %b, double %f) {
 ; CHECK-LABEL: f4:
 ; CHECK: lndbr
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
   %abs = call double @llvm.fabs.f64(double %f)
   %neg = fsub double -0.0, %abs
   %cond = fcmp oeq double %neg, 0.0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Absolute floating-point value.
 ; Test f32
 define float @f5(float %a, float %b, float %f) {
 ; CHECK-LABEL: f5:
 ; CHECK: lpebr
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
   %abs = call float @llvm.fabs.f32(float %f)
   %cond = fcmp oeq float %abs, 0.0
   %res = select i1 %cond, float %a, float %b
   ret float %res
 }
 
 ; Test f64
 define double @f6(double %a, double %b, double %f) {
 ; CHECK-LABEL: f6:
 ; CHECK: lpdbr
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
   %abs = call double @llvm.fabs.f64(double %f)
   %cond = fcmp oeq double %abs, 0.0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

llvm/trunk/test/CodeGen/SystemZ/fp-move-09.ll

; CHECK: br %r14
   %trunc = trunc i32 %res to i8
   store i8 %trunc, i8 *%ptr
   ret void
 }
 
 ; Like f2, but with a conditional store.
 define void @f3(float %val, i8 *%ptr, i32 %which) {
 ; CHECK-LABEL: f3:
-; CHECK: cijlh %r3, 0,
+; CHECK: ciblh %r3, 0, 0(%r14)
+
 ; CHECK: lgdr [[REG:%r[0-5]]], %f0
 ; CHECK: stch [[REG]], 0(%r2)
 ; CHECK: br %r14
   %int = bitcast float %val to i32
   %trunc = trunc i32 %int to i8
   %old = load i8 , i8 *%ptr
   %cmp = icmp eq i32 %which, 0
   %res = select i1 %cmp, i8 %trunc, i8 %old
   store i8 %res, i8 *%ptr
   ret void
 }
 
 ; ...and again with 16-bit memory.
 define void @f4(float %val, i16 *%ptr, i32 %which) {
 ; CHECK-LABEL: f4:
-; CHECK: cijlh %r3, 0,
+; CHECK: ciblh %r3, 0, 0(%r14)
 ; CHECK: lgdr [[REG:%r[0-5]]], %f0
 ; CHECK: sthh [[REG]], 0(%r2)
 ; CHECK: br %r14
   %int = bitcast float %val to i32
   %trunc = trunc i32 %int to i16
   %old = load i16 , i16 *%ptr
   %cmp = icmp eq i32 %which, 0
   %res = select i1 %cmp, i16 %trunc, i16 %old
   store i16 %res, i16 *%ptr
   ret void
 }

llvm/trunk/test/CodeGen/SystemZ/fp-move-10.ll

; CHECK: br %r14
   %trunc = trunc i32 %res to i8
   store i8 %trunc, i8 *%ptr
   ret void
 }
 
 ; Like f2, but with a conditional store.
 define void @f3(float %val, i8 *%ptr, i32 %which) {
 ; CHECK-LABEL: f3:
-; CHECK-DAG: cijlh %r3, 0,
+; CHECK-DAG: ciblh %r3, 0, 0(%r14)
 ; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0
 ; CHECK: stc [[REG]], 0(%r2)
 ; CHECK: br %r14
   %int = bitcast float %val to i32
   %trunc = trunc i32 %int to i8
   %old = load i8, i8 *%ptr
   %cmp = icmp eq i32 %which, 0
   %res = select i1 %cmp, i8 %trunc, i8 %old
   store i8 %res, i8 *%ptr
   ret void
 }
 
 ; ...and again with 16-bit memory.
 define void @f4(float %val, i16 *%ptr, i32 %which) {
 ; CHECK-LABEL: f4:
-; CHECK-DAG: cijlh %r3, 0,
+; CHECK-DAG: ciblh %r3, 0, 0(%r14)
 ; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0
 ; CHECK: sth [[REG]], 0(%r2)
 ; CHECK: br %r14
   %int = bitcast float %val to i32
   %trunc = trunc i32 %int to i16
   %old = load i16, i16 *%ptr
   %cmp = icmp eq i32 %which, 0
   %res = select i1 %cmp, i16 %trunc, i16 %old
   store i16 %res, i16 *%ptr
   ret void
 }

llvm/trunk/test/CodeGen/SystemZ/fp-sqrt-01.ll

; CHECK: br %r14
   ret void
 }
 
 ; Check that a call to the normal sqrtf function is lowered.
 define float @f8(float %dummy, float %val) {
 ; CHECK-LABEL: f8:
 ; CHECK: sqebr %f0, %f2
 ; CHECK: cebr %f0, %f0
-; CHECK: jo [[LABEL:\.L.*]]
-; CHECK: br %r14
-; CHECK: [[LABEL]]:
+; CHECK: bnor %r14
 ; CHECK: ler %f0, %f2
 ; CHECK: jg sqrtf@PLT
   %res = tail call float @sqrtf(float %val)
   ret float %res
 }

llvm/trunk/test/CodeGen/SystemZ/fp-sqrt-02.ll

; CHECK: br %r14
   ret void
 }
 
 ; Check that a call to the normal sqrt function is lowered.
 define double @f8(double %dummy, double %val) {
 ; CHECK-LABEL: f8:
 ; CHECK: sqdbr %f0, %f2
 ; CHECK: cdbr %f0, %f0
-; CHECK: jo [[LABEL:\.L.*]]
-; CHECK: br %r14
-; CHECK: [[LABEL]]:
+; CHECK: bnor %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: jg sqrt@PLT
   %res = tail call double @sqrt(double %val)
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/htm-intrinsics.ll

 }
 
 ; TBEGIN (nofloat) with implicit CC check.
 define void @test_tbegin_nofloat3(i32 *%ptr) {
 ; CHECK-LABEL: test_tbegin_nofloat3:
 ; CHECK-NOT: stmg
 ; CHECK-NOT: std
 ; CHECK: tbegin 0, 65292
-; CHECK: jnh  {{\.L*}}
+; CHECK: bnhr %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
   %cmp = icmp eq i32 %res, 2
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   store i32 0, i32* %ptr, align 4
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
   ret void
 }
 
 ; TBEGIN (nofloat) with dual CC use.
 define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) {
 ; CHECK-LABEL: test_tbegin_nofloat4:
 ; CHECK-NOT: stmg
 ; CHECK-NOT: std
 ; CHECK: tbegin 0, 65292
 ; CHECK: ipm %r2
 ; CHECK: srl %r2, 28
-; CHECK: cijlh %r2, 2,  {{\.L*}}
+; CHECK: ciblh %r2, 2, 0(%r14)
 ; CHECK: mvhi 0(%r3), 0
 ; CHECK: br %r14
   %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
   %cmp = icmp eq i32 %res, 2
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   store i32 0, i32* %ptr, align 4
; CHECK: br %r14
   %res = call i32 @llvm.s390.tend()
   ret i32 %res
 }
 
 ; TEND with implicit CC check.
 define void @test_tend3(i32 *%ptr) {
 ; CHECK-LABEL: test_tend3:
 ; CHECK: tend
-; CHECK: je  {{\.L*}}
+; CHECK: ber %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %res = call i32 @llvm.s390.tend()
   %cmp = icmp eq i32 %res, 2
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   store i32 0, i32* %ptr, align 4
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
   ret void
 }
 
 ; TEND with dual CC use.
 define i32 @test_tend2(i32 %pad, i32 *%ptr) {
 ; CHECK-LABEL: test_tend2:
 ; CHECK: tend
 ; CHECK: ipm %r2
 ; CHECK: srl %r2, 28
-; CHECK: cijlh %r2, 2,  {{\.L*}}
+; CHECK: ciblh %r2, 2, 0(%r14)
 ; CHECK: mvhi 0(%r3), 0
 ; CHECK: br %r14
   %res = call i32 @llvm.s390.tend()
   %cmp = icmp eq i32 %res, 2
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   store i32 0, i32* %ptr, align 4

llvm/trunk/test/CodeGen/SystemZ/int-cmp-01.ll

; CHECK: br %r14
   store i32 %res, i32 *%dst
   ret void
 }
 
 ; Check the comparison can be reversed if that allows CH to be used.
 define double @f11(double %a, double %b, i32 %rhs, i16 *%src) {
 ; CHECK-LABEL: f11:
 ; CHECK: ch %r2, 0(%r3)
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %half = load i16 , i16 *%src
   %lhs = sext i16 %half to i32
   %cond = icmp slt i32 %lhs, %rhs
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-02.ll

 ; Test 32-bit signed comparison in which the second operand is a variable.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 declare i32 @foo()
 
 ; Check register comparison.
 define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
 ; CHECK-LABEL: f1:
-; CHECK: crjl %r2, %r3
+; CHECK: crbl %r2, %r3, 0(%r14)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the C range.
 define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: c %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the aligned C range.
 define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: c %r2, 4092(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 1023
   %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word up, which should use CY instead of C.
 define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f4:
 ; CHECK: cy %r2, 4096(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 1024
   %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the aligned CY range.
 define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f5:
 ; CHECK: cy %r2, 524284(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 131071
   %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: c %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 131072
   %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the negative aligned CY range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f7:
 ; CHECK: cy %r2, -4(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -1
   %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the CY range.
 define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f8:
 ; CHECK: cy %r2, -524288(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -131072
   %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: c %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -131073
   %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that C allows an index.
 define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
 ; CHECK-LABEL: f10:
 ; CHECK: c %r2, 4092({{%r4,%r3|%r3,%r4}})
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4092
   %ptr = inttoptr i64 %add2 to i32 *
   %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CY allows an index.
 define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
 ; CHECK-LABEL: f11:
 ; CHECK: cy %r2, 4096({{%r4,%r3|%r3,%r4}})
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
   %i2 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b

 while.end:
   ret void
 }
 
 ; Check the comparison can be reversed if that allows C to be used.
 define double @f13(double %a, double %b, i32 %i2, i32 *%ptr) {
 ; CHECK-LABEL: f13:
 ; CHECK: c %r2, 0(%r3)
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i1 = load i32 , i32 *%ptr
   %cond = icmp slt i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-03.ll

 ; Test 32-bit unsigned comparison in which the second operand is a variable.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check register comparison.
 define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
 ; CHECK-LABEL: f1:
-; CHECK: clrjl %r2, %r3
+; CHECK: clrbl %r2, %r3, 0(%r14)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the CL range.
 define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cl %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the aligned CL range.
 define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: cl %r2, 4092(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 1023
   %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word up, which should use CLY instead of CL.
 define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f4:
 ; CHECK: cly %r2, 4096(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 1024
   %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the aligned CLY range.
 define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f5:
 ; CHECK: cly %r2, 524284(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 131071
   %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cl %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 131072
   %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the negative aligned CLY range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f7:
 ; CHECK: cly %r2, -4(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -1
   %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the CLY range.
 define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f8:
 ; CHECK: cly %r2, -524288(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -131072
   %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: cl %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -131073
   %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CL allows an index.
 define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
 ; CHECK-LABEL: f10:
 ; CHECK: cl %r2, 4092({{%r4,%r3|%r3,%r4}})
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4092
   %ptr = inttoptr i64 %add2 to i32 *
   %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CLY allows an index.
 define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
 ; CHECK-LABEL: f11:
 ; CHECK: cly %r2, 4096({{%r4,%r3|%r3,%r4}})
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 4096
   %ptr = inttoptr i64 %add2 to i32 *
   %i2 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the comparison can be reversed if that allows CL to be used.
 define double @f12(double %a, double %b, i32 %i2, i32 *%ptr) {
 ; CHECK-LABEL: f12:
 ; CHECK: cl %r2, 0(%r3)
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i1 = load i32 , i32 *%ptr
   %cond = icmp ult i32 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-04.ll

; CHECK: br %r14
   store i64 %res, i64 *%dst
   ret void
 }
 
 ; Check the comparison can be reversed if that allows CGH to be used.
 define double @f8(double %a, double %b, i64 %rhs, i16 *%src) {
 ; CHECK-LABEL: f8:
 ; CHECK: cgh %r2, 0(%r3)
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %half = load i16 , i16 *%src
   %lhs = sext i16 %half to i64
   %cond = icmp slt i64 %lhs, %rhs
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-05.ll

 ; Test 64-bit comparison in which the second operand is a sign-extended i32.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 declare i64 @foo()
 
 ; Check signed register comparison.
 define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
 ; CHECK-LABEL: f1:
 ; CHECK: cgfr %r2, %r3
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned register comparison, which can't use CGFR.
 define double @f2(double %a, double %b, i64 %i1, i32 %unext) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: cgfr
 ; CHECK: br %r14
   %i2 = sext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check register equality.
 define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
 ; CHECK-LABEL: f3:
 ; CHECK: cgfr %r2, %r3
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = sext i32 %unext to i64
   %cond = icmp eq i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check register inequality.
 define double @f4(double %a, double %b, i64 %i1, i32 %unext) {
 ; CHECK-LABEL: f4:
 ; CHECK: cgfr %r2, %r3
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = sext i32 %unext to i64
   %cond = icmp ne i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check signed comparison with memory.
 define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: cgf %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check memory equality.
 define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK: cgf %r2, 0(%r3)
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp eq i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check memory inequality.
 define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: cgf %r2, 0(%r3)
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp ne i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the aligned CGF range.
 define double @f9(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-LABEL: f9:
 ; CHECK: cgf %r2, 524284(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 131071
   %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f10(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-LABEL: f10:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cgf %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 131072
   %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the negative aligned CGF range.
 define double @f11(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-LABEL: f11:
 ; CHECK: cgf %r2, -4(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -1
   %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the CGF range.
 define double @f12(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-LABEL: f12:
 ; CHECK: cgf %r2, -524288(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -131072
   %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-LABEL: f13:
 ; CHECK: agfi %r3, -524292
 ; CHECK: cgf %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -131073
   %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CGF allows an index.
 define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
 ; CHECK-LABEL: f14:
 ; CHECK: cgf %r2, 524284({{%r4,%r3|%r3,%r4}})
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 524284
   %ptr = inttoptr i64 %add2 to i32 *
   %unext = load i32 , i32 *%ptr
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
; CHECK: br %r14
 
   ret i64 %sel9
 }
 
 ; Check the comparison can be reversed if that allows CGFR to be used.
 define double @f16(double %a, double %b, i64 %i1, i32 %unext) {
 ; CHECK-LABEL: f16:
 ; CHECK: cgfr %r2, %r3
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = sext i32 %unext to i64
   %cond = icmp slt i64 %i2, %i1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Likewise CGF.
 define double @f17(double %a, double %b, i64 %i2, i32 *%ptr) {
 ; CHECK-LABEL: f17:
 ; CHECK: cgf %r2, 0(%r3)
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %unext = load i32 , i32 *%ptr
   %i1 = sext i32 %unext to i64
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-06.ll

 ; Test 64-bit comparison in which the second operand is a zero-extended i32.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 declare i64 @foo()
 
 ; Check unsigned register comparison.
 define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
 ; CHECK-LABEL: f1:
 ; CHECK: clgfr %r2, %r3
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; ...and again with a different representation.
 define double @f2(double %a, double %b, i64 %i1, i64 %unext) {
 ; CHECK-LABEL: f2:
 ; CHECK: clgfr %r2, %r3
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = and i64 %unext, 4294967295
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check register equality.
 define double @f5(double %a, double %b, i64 %i1, i32 %unext) {
 ; CHECK-LABEL: f5:
 ; CHECK: clgfr %r2, %r3
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = zext i32 %unext to i64
   %cond = icmp eq i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; ...and again with a different representation
 define double @f6(double %a, double %b, i64 %i1, i64 %unext) {
 ; CHECK-LABEL: f6:
 ; CHECK: clgfr %r2, %r3
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = and i64 %unext, 4294967295
   %cond = icmp eq i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check register inequality.
 define double @f7(double %a, double %b, i64 %i1, i32 %unext) {
 ; CHECK-LABEL: f7:
 ; CHECK: clgfr %r2, %r3
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = zext i32 %unext to i64
   %cond = icmp ne i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; ...and again with a different representation
 define double @f8(double %a, double %b, i64 %i1, i64 %unext) {
 ; CHECK-LABEL: f8:
 ; CHECK: clgfr %r2, %r3
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = and i64 %unext, 4294967295
   %cond = icmp ne i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison with memory.
 define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: clgf %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check memory equality.
 define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK: clgf %r2, 0(%r3)
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp eq i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check memory inequality.
 define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) {
 ; CHECK-LABEL: f12:
 ; CHECK: clgf %r2, 0(%r3)
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ne i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the aligned CLGF range.
 define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-LABEL: f13:
 ; CHECK: clgf %r2, 524284(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 131071
   %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f14(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-LABEL: f14:
 ; CHECK: agfi %r3, 524288
 ; CHECK: clgf %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 131072
   %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the negative aligned CLGF range.
 define double @f15(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-LABEL: f15:
 ; CHECK: clgf %r2, -4(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -1
   %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the CLGF range.
 define double @f16(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-LABEL: f16:
 ; CHECK: clgf %r2, -524288(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -131072
   %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f17(double %a, double %b, i64 %i1, i32 *%base) {
 ; CHECK-LABEL: f17:
 ; CHECK: agfi %r3, -524292
 ; CHECK: clgf %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -131073
   %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CLGF allows an index.
 define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
 ; CHECK-LABEL: f18:
 ; CHECK: clgf %r2, 524284({{%r4,%r3|%r3,%r4}})
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 524284
   %ptr = inttoptr i64 %add2 to i32 *
   %unext = load i32 , i32 *%ptr
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
; CHECK: br %r14
 
   ret i64 %sel9
 }
 
 ; Check the comparison can be reversed if that allows CLGFR to be used.
 define double @f20(double %a, double %b, i64 %i1, i32 %unext) {
 ; CHECK-LABEL: f20:
 ; CHECK: clgfr %r2, %r3
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = zext i32 %unext to i64
   %cond = icmp ult i64 %i2, %i1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; ...and again with the AND representation.
 define double @f21(double %a, double %b, i64 %i1, i64 %unext) {
 ; CHECK-LABEL: f21:
 ; CHECK: clgfr %r2, %r3
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = and i64 %unext, 4294967295
   %cond = icmp ult i64 %i2, %i1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the comparison can be reversed if that allows CLGF to be used.
 define double @f22(double %a, double %b, i64 %i2, i32 *%ptr) {
 ; CHECK-LABEL: f22:
 ; CHECK: clgf %r2, 0(%r3)
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %unext = load i32 , i32 *%ptr
   %i1 = zext i32 %unext to i64
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-07.ll

 ; Test 64-bit signed comparison in which the second operand is a variable.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check CGR.
 define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
 ; CHECK-LABEL: f1:
-; CHECK: cgrjl %r2, %r3
+; CHECK: cgrbl %r2, %r3, 0(%r14)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check CG with no displacement.
 define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cg %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the aligned CG range.
 define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: cg %r2, 524280(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 65535
   %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cg %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 65536
   %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the negative aligned CG range.
 define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f5:
 ; CHECK: cg %r2, -8(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 -1
   %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the CG range.
 define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f6:
 ; CHECK: cg %r2, -524288(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 -65536
   %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: cg %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 -65537
   %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CG allows an index.
 define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
 ; CHECK-LABEL: f8:
 ; CHECK: cg %r2, 524280({{%r4,%r3|%r3,%r4}})
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 524280
   %ptr = inttoptr i64 %add2 to i64 *
   %i2 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the comparison can be reversed if that allows CG to be used.
 define double @f9(double %a, double %b, i64 %i2, i64 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: cg %r2, 0(%r3)
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i1 = load i64 , i64 *%ptr
   %cond = icmp slt i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-08.ll

 ; Test 64-bit unsigned comparison in which the second operand is a variable.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check CLGR.
 define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
 ; CHECK-LABEL: f1:
-; CHECK: clgrjl %r2, %r3
+; CHECK: clgrbl %r2, %r3, 0(%r14)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check CLG with no displacement.
 define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clg %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the aligned CLG range.
 define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: clg %r2, 524280(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 65535
   %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: clg %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 65536
   %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the negative aligned CLG range.
 define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f5:
 ; CHECK: clg %r2, -8(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 -1
   %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the CLG range.
 define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f6:
 ; CHECK: clg %r2, -524288(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 -65536
   %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: clg %r2, 0(%r3)
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 -65537
   %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CLG allows an index.
 define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
 ; CHECK-LABEL: f8:
 ; CHECK: clg %r2, 524280({{%r4,%r3|%r3,%r4}})
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 524280
   %ptr = inttoptr i64 %add2 to i64 *
   %i2 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the comparison can be reversed if that allows CLG to be used.
 define double @f9(double %a, double %b, i64 %i2, i64 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: clg %r2, 0(%r3)
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %i1 = load i64 , i64 *%ptr
   %cond = icmp ult i64 %i1, %i2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-09.ll

 ; Test 32-bit signed comparison in which the second operand is constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f1:
 ; CHECK: cijl %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, 0
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check comparisons with 2.
 define double @f2(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f2:
 ; CHECK: cijl %r2, 2
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, 2
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CIJ range.
 define double @f3(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f3:
 ; CHECK: cijl %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, 127
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which must use CHI instead.
 define double @f4(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f4:
 ; CHECK: chi %r2, 128
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, 128
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CHI range.
 define double @f5(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f5:
 ; CHECK: chi %r2, 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, 32767
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which must use CFI.
 define double @f6(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f6:
 ; CHECK: cfi %r2, 32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, 32768
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the signed 32-bit range.
 define double @f7(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f7:
 ; CHECK: cfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i32 %i1, 2147483647
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which should be treated as a negative value.
 define double @f8(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f8:
 ; CHECK: cfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i32 %i1, 2147483648
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the negative CIJ range.
 define double @f9(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f9:
 ; CHECK: cijl %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, -1
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the CIJ range.
 define double @f10(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f10:
 ; CHECK: cijl %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, -128
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which must use CHI instead.
 define double @f11(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f11:
 ; CHECK: chi %r2, -129
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, -129
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the CHI range.
 define double @f12(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f12:
 ; CHECK: chi %r2, -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, -32768
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which must use CFI instead.
 define double @f13(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f13:
 ; CHECK: cfi %r2, -32769
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, -32769
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the signed 32-bit range.
 define double @f14(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f14:
 ; CHECK: cfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i32 %i1, -2147483648
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f15(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f15:
 ; CHECK: cfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i32 %i1, -2147483649
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check that < 1 becomes <= 0.
 define double @f16(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f16:
 ; CHECK: cijle %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i32 %i1, 1
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check that >= 1 becomes > 0.
 define double @f17(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f17:
 ; CHECK: cijh %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp sge i32 %i1, 1
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check that > -1 becomes >= 0.
 define double @f18(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f18:
 ; CHECK: cijhe %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp sgt i32 %i1, -1
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check that <= -1 becomes < 0.
 define double @f19(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f19:
 ; CHECK: cijl %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp sle i32 %i1, -1
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-10.ll

 ; Test 32-bit unsigned comparisons in which the second operand is constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check a value near the low end of the range.  We use signed forms for
 ; comparisons with zero, or things that are equivalent to them.
 define double @f1(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f1:
 ; CHECK: clijh %r2, 1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ugt i32 %i1, 1
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the top of the CLIJ range.
 define double @f2(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f2:
 ; CHECK: clijl %r2, 255
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ult i32 %i1, 255
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which needs a separate comparison.
 define double @f3(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f3:
 ; CHECK: clfi %r2, 256
 ; CHECK: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ult i32 %i1, 256
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check a value near the high end of the range.
 define double @f4(double %a, double %b, i32 %i1) {
 ; CHECK-LABEL: f4:
 ; CHECK: clfi %r2, 4294967280
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ult i32 %i1, 4294967280
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-11.ll

 ; Test 64-bit signed comparisons in which the second operand is a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f1:
 ; CHECK: cgijl %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, 0
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check comparisons with 1.
 define double @f2(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f2:
 ; CHECK: cgijle %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, 1
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CGIJ range.
 define double @f3(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f3:
 ; CHECK: cgijl %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, 127
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which must use CGHI instead.
 define double @f4(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, 128
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CGHI range.
 define double @f5(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f5:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, 32767
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which must use CGFI.
 define double @f6(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, 32768
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CGFI range.
 define double @f7(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f7:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, 2147483647
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which must use register comparison.
 define double @f8(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f8:
 ; CHECK: cgrjl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, 2147483648
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the negative CGIJ range.
 define double @f9(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f9:
 ; CHECK: cgijl %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, -1
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f10:
 ; CHECK: cgijl %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, -128
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which must use CGHI instead.
 define double @f11(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f11:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, -129
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the CGHI range.
 define double @f12(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, -32768
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which must use CGFI instead.
 define double @f13(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f13:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, -32769
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the CGFI range.
 define double @f14(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, -2147483648
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which must use register comparison.
 define double @f15(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f15:
 ; CHECK: cgrjl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, -2147483649
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-12.ll

 ; Test 64-bit unsigned comparisons in which the second operand is constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check a value near the low end of the range.  We use signed forms for
 ; comparisons with zero, or things that are equivalent to them.
 define double @f1(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f1:
 ; CHECK: clgijh %r2, 1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ugt i64 %i1, 1
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the top of the CLGIJ range.
 define double @f2(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f2:
 ; CHECK: clgijl %r2, 255
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ult i64 %i1, 255
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which needs a separate comparison.
 define double @f3(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f3:
 ; CHECK: clgfi %r2, 256
 ; CHECK: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ult i64 %i1, 256
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CLGFI range.
 define double @f4(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f4:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ult i64 %i1, 4294967295
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which can use a shifted comparison
 define double @f5(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f5:
 ; CHECK: srlg [[REG:%r[0-5]]], %r2, 32
 ; CHECK: cgije [[REG]], 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ult i64 %i1, 4294967296
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 ; Check the next value up, which must use a register comparison.
 define double @f6(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f6:
 ; CHECK: clgrjl %r2,
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ult i64 %i1, 4294967297
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-13.ll

 ; Test 64-bit equality comparisons in which the second operand is a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f1:
 ; CHECK: cgije %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, 0
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CGIJ range.
 define double @f2(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f2:
 ; CHECK: cgije %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, 127
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which must use CGHI instead.
 define double @f3(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f3:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, 128
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CGHI range.
 define double @f4(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, 32767
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which must use CGFI.
 define double @f5(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f5:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, 32768
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CGFI range.
 define double @f6(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, 2147483647
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which should use CLGFI instead.
 define double @f7(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f7:
 ; CHECK: clgfi %r2, 2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, 2147483648
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CLGFI range.
 define double @f8(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f8:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, 4294967295
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which must use a register comparison.
 define double @f9(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f9:
 ; CHECK: cgrje %r2,
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, 4294967296
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the negative CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f10:
 ; CHECK: cgije %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, -1
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the CGIJ range.
 define double @f11(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f11:
 ; CHECK: cgije %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, -128
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which must use CGHI instead.
 define double @f12(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, -129
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the CGHI range.
 define double @f13(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f13:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, -32768
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which must use CGFI instead.
 define double @f14(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, -32769
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the CGFI range.
 define double @f15(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f15:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, -2147483648
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which must use register comparison.
 define double @f16(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f16:
 ; CHECK: cgrje
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp eq i64 %i1, -2147483649
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-14.ll

 ; Test 64-bit inequality comparisons in which the second operand is a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f1:
 ; CHECK: cgijlh %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, 0
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CGIJ range.
 define double @f2(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f2:
 ; CHECK: cgijlh %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, 127
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which must use CGHI instead.
 define double @f3(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f3:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, 128
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CGHI range.
 define double @f4(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, 32767
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which must use CGFI.
 define double @f5(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f5:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, 32768
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CGFI range.
 define double @f6(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, 2147483647
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which should use CLGFI instead.
 define double @f7(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f7:
 ; CHECK: clgfi %r2, 2147483648
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, 2147483648
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the CLGFI range.
 define double @f8(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f8:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, 4294967295
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value up, which must use a register comparison.
 define double @f9(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f9:
 ; CHECK: cgrjlh %r2,
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, 4294967296
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the high end of the negative CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f10:
 ; CHECK: cgijlh %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, -1
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the CGIJ range.
 define double @f11(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f11:
 ; CHECK: cgijlh %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, -128
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which must use CGHI instead.
 define double @f12(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, -129
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the CGHI range.
 define double @f13(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f13:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, -32768
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which must use CGFI instead.
 define double @f14(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, -32769
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the low end of the CGFI range.
 define double @f15(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f15:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, -2147483648
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }
 
 ; Check the next value down, which must use register comparison.
 define double @f16(double %a, double %b, i64 %i1) {
 ; CHECK-LABEL: f16:
 ; CHECK: cgrjlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp ne i64 %i1, -2147483649
-  %res = select i1 %cond, double %a, double %b
+  %tmp = select i1 %cond, double %a, double %b
+  %res = fadd double %tmp, 1.0
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-15.ll

 ; Test 8-bit unsigned comparisons between memory and constants.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check ordered comparisons near the low end of the unsigned 8-bit range.
 define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %cond = icmp ugt i8 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check ordered comparisons near the high end of the unsigned 8-bit range.
 define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 254
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %cond = icmp ult i8 %val, 254
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check tests for negative bytes.
 define double @f3(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 127
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %cond = icmp slt i8 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; ...and an alternative form.
 define double @f4(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 127
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %cond = icmp sle i8 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check tests for non-negative bytes.
 define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 128
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %cond = icmp sge i8 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; ...and an alternative form.
 define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 128
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %cond = icmp sgt i8 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons at the low end of the signed 8-bit range.
 define double @f7(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK: cli 0(%r2), 128
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %cond = icmp eq i8 %val, -128
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons at the low end of the unsigned 8-bit range.
 define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %cond = icmp eq i8 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons at the high end of the signed 8-bit range.
 define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 127
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %cond = icmp eq i8 %val, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons at the high end of the unsigned 8-bit range.
 define double @f10(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 255
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %cond = icmp eq i8 %val, 255
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the CLI range.

llvm/trunk/test/CodeGen/SystemZ/int-cmp-16.ll

 ; Test 32-bit equality comparisons that are really between a memory byte
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp eq i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp eq i32 %ext, 255
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp eq i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp eq i32 %ext, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp eq i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp eq i32 %ext, -128
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

llvm/trunk/test/CodeGen/SystemZ/int-cmp-17.ll

 ; Test 32-bit inequality comparisons that are really between a memory byte
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp ne i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp ne i32 %ext, 255
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ne i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ne i32 %ext, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ne i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ne i32 %ext, -128
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

llvm/trunk/test/CodeGen/SystemZ/int-cmp-18.ll

 ; Test 64-bit equality comparisons that are really between a memory byte
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp eq i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp eq i64 %ext, 255
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp eq i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp eq i64 %ext, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp eq i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp eq i64 %ext, -128
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

llvm/trunk/test/CodeGen/SystemZ/int-cmp-19.ll

 ; Test 64-bit inequality comparisons that are really between a memory byte
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp ne i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp ne i64 %ext, 255
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ne i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ne i64 %ext, 127
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ne i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ne i64 %ext, -128
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

llvm/trunk/test/CodeGen/SystemZ/int-cmp-20.ll

 ; Test 32-bit ordered comparisons that are really between a memory byte
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check unsigned comparison near the low end of the CLI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp ugt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the low end of the CLI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ugt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the high end of the CLI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 254
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp ult i32 %ext, 254
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the high end of the CLI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 254
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp ult i32 %ext, -2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   ret double %res
 }
 
 ; Check signed comparison near the low end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp sgt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   ret double %res
 }
 
 ; Check signed comparison near the high end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 254
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i32
   %cond = icmp slt i32 %ext, 254
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check tests for nonnegative values.
 define double @f13(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f13:
 ; CHECK: cli 0(%r2), 128
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp sge i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; ...and another form
 define double @f14(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f14:
 ; CHECK: cli 0(%r2), 128
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp sgt i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check tests for negative values.
 define double @f15(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f15:
 ; CHECK: cli 0(%r2), 127
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp slt i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; ...and another form
 define double @f16(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f16:
 ; CHECK: cli 0(%r2), 127
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i32
   %cond = icmp sle i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-21.ll

 ; Test 64-bit ordered comparisons that are really between a memory byte
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check unsigned comparison near the low end of the CLI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp ugt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the low end of the CLI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ugt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the high end of the CLI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 254
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp ult i64 %ext, 254
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the high end of the CLI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 254
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp ult i64 %ext, -2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   ret double %res
 }
 
 ; Check signed comparison near the low end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp sgt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   ret double %res
 }
 
 ; Check signed comparison near the high end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 254
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = zext i8 %val to i64
   %cond = icmp slt i64 %ext, 254
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check tests for nonnegative values.
 define double @f13(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f13:
 ; CHECK: cli 0(%r2), 128
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp sge i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; ...and another form
 define double @f14(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f14:
 ; CHECK: cli 0(%r2), 128
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp sgt i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check tests for negative values.
 define double @f15(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f15:
 ; CHECK: cli 0(%r2), 127
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp slt i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; ...and another form
 define double @f16(double %a, double %b, i8 *%ptr) {
 ; CHECK-LABEL: f16:
 ; CHECK: cli 0(%r2), 127
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i8 , i8 *%ptr
   %ext = sext i8 %val to i64
   %cond = icmp sle i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-22.ll

 ; Test 16-bit signed ordered comparisons between memory and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: chhsi 0(%r2), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with 1.
 define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: chhsi 0(%r2), 0
-; CHECK-NEXT: jle
+; CHECK-NEXT: bler %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check a value near the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: chhsi 0(%r2), 32766
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 32766
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with -1.
 define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: chhsi 0(%r2), -1
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check a value near the low end of the 16-bit signed range.
 define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: chhsi 0(%r2), -32766
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, -32766
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the CHHSI range.
 define double @f6(double %a, double %b, i16 %i1, i16 *%base) {
 ; CHECK-LABEL: f6:
 ; CHECK: chhsi 4094(%r3), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 2047
   %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next halfword up, which needs separate address logic,
 define double @f7(double %a, double %b, i16 *%base) {
 ; CHECK-LABEL: f7:
 ; CHECK: aghi %r2, 4096
 ; CHECK: chhsi 0(%r2), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 2048
   %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check negative offsets, which also need separate address logic.
 define double @f8(double %a, double %b, i16 *%base) {
 ; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, -2
 ; CHECK: chhsi 0(%r2), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 -1
   %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CHHSI does not allow indices.
 define double @f9(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK-LABEL: f9:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: chhsi 0({{%r[23]}}), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i16 *
   %val = load i16 , i16 *%ptr
   %cond = icmp slt i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-23.ll

 ; Test 16-bit unsigned comparisons between memory and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check a value near the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp ugt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check a value near the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65534
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp ult i16 %val, 65534
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the CLHHSI range.
 define double @f3(double %a, double %b, i16 %i1, i16 *%base) {
 ; CHECK-LABEL: f3:
 ; CHECK: clhhsi 4094(%r3), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 2047
   %val = load i16 , i16 *%ptr
   %cond = icmp ugt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next halfword up, which needs separate address logic,
 define double @f4(double %a, double %b, i16 *%base) {
 ; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clhhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 2048
   %val = load i16 , i16 *%ptr
   %cond = icmp ugt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check negative offsets, which also need separate address logic.
 define double @f5(double %a, double %b, i16 *%base) {
 ; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -2
 ; CHECK: clhhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i16, i16 *%base, i64 -1
   %val = load i16 , i16 *%ptr
   %cond = icmp ugt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CLHHSI does not allow indices.
 define double @f6(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK-LABEL: f6:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clhhsi 0({{%r[23]}}), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i16 *
   %val = load i16 , i16 *%ptr
   %cond = icmp ugt i16 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-24.ll

 ; Test 16-bit equality comparisons between memory and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp eq i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp eq i16 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 32768
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp eq i16 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the signed 16-bit range.
 define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 32767
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp eq i16 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-25.ll

 ; Test 16-bit inequality comparisons between memory and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp ne i16 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp ne i16 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 32768
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp ne i16 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the signed 16-bit range.
 define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 32767
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %cond = icmp ne i16 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-26.ll

 ; Test 32-bit equality comparisons that are really between a memory halfword
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp eq i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp eq i32 %ext, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp eq i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp eq i32 %ext, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp eq i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp eq i32 %ext, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

llvm/trunk/test/CodeGen/SystemZ/int-cmp-27.ll

 ; Test 32-bit inequality comparisons that are really between a memory halfword
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp ne i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp ne i32 %ext, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ne i32 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ne i32 %ext, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ne i32 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ne i32 %ext, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

llvm/trunk/test/CodeGen/SystemZ/int-cmp-28.ll

 ; Test 64-bit equality comparisons that are really between a memory halfword
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp eq i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp eq i64 %ext, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp eq i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp eq i64 %ext, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp eq i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp eq i64 %ext, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

llvm/trunk/test/CodeGen/SystemZ/int-cmp-29.ll

 ; Test 64-bit inequality comparisons that are really between a memory halfword
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp ne i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp ne i64 %ext, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ne i64 %ext, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ne i64 %ext, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ne i64 %ext, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ne i64 %ext, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

llvm/trunk/test/CodeGen/SystemZ/int-cmp-30.ll

 ; Test 32-bit ordered comparisons that are really between a memory halfword
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check unsigned comparison near the low end of the CLHHSI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp ugt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the low end of the CLHHSI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ugt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the high end of the CLHHSI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 65534
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp ult i32 %ext, 65534
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the high end of the CLHHSI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 65534
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp ult i32 %ext, -2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   ret double %res
 }
 
 ; Check signed comparison near the low end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp sgt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check signed comparison near the low end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: chhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp sgt i32 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check signed comparison near the high end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: clhhsi 0(%r2), 65534
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i32
   %cond = icmp slt i32 %ext, 65534
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check signed comparison near the high end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f11(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK: chhsi 0(%r2), -2
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp slt i32 %ext, -2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   ret double %res
 }
 
 ; Check signed comparison near the high end of the CHHSI range, using sign
 ; extension.
 define double @f13(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f13:
 ; CHECK: chhsi 0(%r2), 32766
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp slt i32 %ext, 32766
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   ret double %res
 }
 
 ; Check signed comparison near the low end of the CHHSI range, using sign
 ; extension.
 define double @f15(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f15:
 ; CHECK: chhsi 0(%r2), -32767
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i32
   %cond = icmp sgt i32 %ext, -32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

llvm/trunk/test/CodeGen/SystemZ/int-cmp-31.ll

 ; Test 64-bit ordered comparisons that are really between a memory halfword
 ; and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check unsigned comparison near the low end of the CLHHSI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp ugt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the low end of the CLHHSI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ugt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the high end of the CLHHSI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 65534
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp ult i64 %ext, 65534
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check unsigned comparison near the high end of the CLHHSI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 65534
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp ult i64 %ext, -2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   ret double %res
 }
 
 ; Check signed comparison near the low end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp sgt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check signed comparison near the low end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f9(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: chhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp sgt i64 %ext, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check signed comparison near the high end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: clhhsi 0(%r2), 65534
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = zext i16 %val to i64
   %cond = icmp slt i64 %ext, 65534
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check signed comparison near the high end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f11(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK: chhsi 0(%r2), -2
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp slt i64 %ext, -2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   ret double %res
 }
 
 ; Check signed comparison near the high end of the CHHSI range, using sign
 ; extension.
 define double @f13(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f13:
 ; CHECK: chhsi 0(%r2), 32766
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp slt i64 %ext, 32766
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
; CHECK: br %r14
   ret double %res
 }
 
 ; Check signed comparison near the low end of the CHHSI range, using sign
 ; extension.
 define double @f15(double %a, double %b, i16 *%ptr) {
 ; CHECK-LABEL: f15:
 ; CHECK: chhsi 0(%r2), -32767
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
   %val = load i16 , i16 *%ptr
   %ext = sext i16 %val to i64
   %cond = icmp sgt i64 %ext, -32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 

llvm/trunk/test/CodeGen/SystemZ/int-cmp-32.ll

 ; Test 32-bit signed comparisons between memory and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check ordered comparisons with 0.
 define double @f1(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: chsi 0(%r2), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check ordered comparisons with 1.
 define double @f2(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: chsi 0(%r2), 0
-; CHECK-NEXT: jle
+; CHECK-NEXT: bler %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check ordered comparisons with the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: chsi 0(%r2), 32767
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value up, which can't use CHSI.
 define double @f4(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check ordered comparisons with -1.
 define double @f5(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: chsi 0(%r2), -1
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check ordered comparisons with the low end of the 16-bit signed range.
 define double @f6(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: chsi 0(%r2), -32768
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value down, which can't use CHSI.
 define double @f7(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, -32769
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with 0.
 define double @f8(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: chsi 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with 1.
 define double @f9(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: chsi 0(%r2), 1
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with the high end of the signed 16-bit range.
 define double @f10(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: chsi 0(%r2), 32767
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value up, which can't use CHSI.
 define double @f11(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with -1.
 define double @f12(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f12:
 ; CHECK: chsi 0(%r2), -1
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with the low end of the 16-bit signed range.
 define double @f13(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f13:
 ; CHECK: chsi 0(%r2), -32768
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f14(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f14:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, -32769
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the CHSI range.
 define double @f15(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f15:
 ; CHECK: chsi 4092(%r3), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 1023
   %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word up, which needs separate address logic,
 define double @f16(double %a, double %b, i32 *%base) {
 ; CHECK-LABEL: f16:
 ; CHECK: aghi %r2, 4096
 ; CHECK: chsi 0(%r2), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 1024
   %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check negative offsets, which also need separate address logic.
 define double @f17(double %a, double %b, i32 *%base) {
 ; CHECK-LABEL: f17:
 ; CHECK: aghi %r2, -4
 ; CHECK: chsi 0(%r2), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -1
   %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CHSI does not allow indices.
 define double @f18(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK-LABEL: f18:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: chsi 0({{%r[23]}}), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
   %val = load i32 , i32 *%ptr
   %cond = icmp slt i32 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-33.ll

 ; Test 32-bit unsigned comparisons between memory and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check ordered comparisons with a constant near the low end of the unsigned
 ; 16-bit range.
 define double @f1(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: clfhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp ugt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check ordered comparisons with the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clfhsi 0(%r2), 65535
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp ult i32 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value up, which can't use CLFHSI.
 define double @f3(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: clfhsi
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp ult i32 %val, 65536
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with 32768, the lowest value for which
 ; we prefer CLFHSI to CHSI.
 define double @f4(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: clfhsi 0(%r2), 32768
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with the high end of the unsigned 16-bit range.
 define double @f5(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: clfhsi 0(%r2), 65535
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value up, which can't use CLFHSI.
 define double @f6(double %a, double %b, i32 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: clfhsi
 ; CHECK: br %r14
   %val = load i32 , i32 *%ptr
   %cond = icmp eq i32 %val, 65536
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the CLFHSI range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 ; CHECK-LABEL: f7:
 ; CHECK: clfhsi 4092(%r3), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 1023
   %val = load i32 , i32 *%ptr
   %cond = icmp ugt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next word up, which needs separate address logic,
 define double @f8(double %a, double %b, i32 *%base) {
 ; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clfhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 1024
   %val = load i32 , i32 *%ptr
   %cond = icmp ugt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check negative offsets, which also need separate address logic.
 define double @f9(double %a, double %b, i32 *%base) {
 ; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -4
 ; CHECK: clfhsi 0(%r2), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i32, i32 *%base, i64 -1
   %val = load i32 , i32 *%ptr
   %cond = icmp ugt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CLFHSI does not allow indices.
 define double @f10(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK-LABEL: f10:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clfhsi 0({{%r[23]}}), 1
-; CHECK-NEXT: jh
+; CHECK-NEXT: bhr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
   %val = load i32 , i32 *%ptr
   %cond = icmp ugt i32 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-34.ll

 ; Test 64-bit signed comparisons between memory and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check ordered comparisons with 0.
 define double @f1(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: cghsi 0(%r2), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check ordered comparisons with 1.
 define double @f2(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: cghsi 0(%r2), 0
-; CHECK-NEXT: jle
+; CHECK-NEXT: bler %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check ordered comparisons with the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK: cghsi 0(%r2), 32767
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value up, which can't use CGHSI.
 define double @f4(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check ordered comparisons with -1.
 define double @f5(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: cghsi 0(%r2), -1
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check ordered comparisons with the low end of the 16-bit signed range.
 define double @f6(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK: cghsi 0(%r2), -32768
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f7(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f7:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, -32769
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with 0.
 define double @f8(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f8:
 ; CHECK: cghsi 0(%r2), 0
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with 1.
 define double @f9(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f9:
 ; CHECK: cghsi 0(%r2), 1
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with the high end of the signed 16-bit range.
 define double @f10(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f10:
 ; CHECK: cghsi 0(%r2), 32767
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 32767
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value up, which can't use CGHSI.
 define double @f11(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f11:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with -1.
 define double @f12(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f12:
 ; CHECK: cghsi 0(%r2), -1
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, -1
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with the low end of the 16-bit signed range.
 define double @f13(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f13:
 ; CHECK: cghsi 0(%r2), -32768
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, -32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f14(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f14:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, -32769
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the CGHSI range.
 define double @f15(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f15:
 ; CHECK: cghsi 4088(%r3), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 511
   %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next doubleword up, which needs separate address logic,
 define double @f16(double %a, double %b, i64 *%base) {
 ; CHECK-LABEL: f16:
 ; CHECK: aghi %r2, 4096
 ; CHECK: cghsi 0(%r2), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 512
   %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check negative offsets, which also need separate address logic.
 define double @f17(double %a, double %b, i64 *%base) {
 ; CHECK-LABEL: f17:
 ; CHECK: aghi %r2, -8
 ; CHECK: cghsi 0(%r2), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 -1
   %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CGHSI does not allow indices.
 define double @f18(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK-LABEL: f18:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: cghsi 0({{%r[23]}}), 0
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i64 *
   %val = load i64 , i64 *%ptr
   %cond = icmp slt i64 %val, 0
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-35.ll

 ; Test 64-bit unsigned comparisons between memory and a constant.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Check ordered comparisons with a constant near the low end of the unsigned
 ; 16-bit range.
 define double @f1(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f1:
 ; CHECK: clghsi 0(%r2), 2
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check ordered comparisons with the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f2:
 ; CHECK: clghsi 0(%r2), 65535
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value up, which can't use CLGHSI.
 define double @f3(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f3:
 ; CHECK-NOT: clghsi
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 65536
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with 32768, the lowest value for which
 ; we prefer CLGHSI to CGHSI.
 define double @f4(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f4:
 ; CHECK: clghsi 0(%r2), 32768
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 32768
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check equality comparisons with the high end of the unsigned 16-bit range.
 define double @f5(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f5:
 ; CHECK: clghsi 0(%r2), 65535
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 65535
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next value up, which can't use CLGHSI.
 define double @f6(double %a, double %b, i64 *%ptr) {
 ; CHECK-LABEL: f6:
 ; CHECK-NOT: clghsi
 ; CHECK: br %r14
   %val = load i64 , i64 *%ptr
   %cond = icmp eq i64 %val, 65536
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the CLGHSI range.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 ; CHECK-LABEL: f7:
 ; CHECK: clghsi 4088(%r3), 2
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 511
   %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the next doubleword up, which needs separate address logic,
 define double @f8(double %a, double %b, i64 *%base) {
 ; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clghsi 0(%r2), 2
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 512
   %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check negative offsets, which also need separate address logic.
 define double @f9(double %a, double %b, i64 *%base) {
 ; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -8
 ; CHECK: clghsi 0(%r2), 2
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %ptr = getelementptr i64, i64 *%base, i64 -1
   %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check that CLGHSI does not allow indices.
 define double @f10(double %a, double %b, i64 %base, i64 %index) {
 ; CHECK-LABEL: f10:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clghsi 0({{%r[23]}}), 2
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i64 *
   %val = load i64 , i64 *%ptr
   %cond = icmp ult i64 %val, 2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-36.ll

 ; Test 32-bit comparisons in which the second operand is sign-extended
 ; from a PC-relative i16.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 @g = global i16 1
 @h = global i16 1, align 1, section "foo"
 
 ; Check signed comparison.
 define i32 @f1(i32 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: chrl %r2, g
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i32
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
exit:
   %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }
 
 ; Check equality.
 define i32 @f3(i32 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: chrl %r2, g
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i32
   %cond = icmp eq i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
   %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }
 
 ; Check inequality.
 define i32 @f4(i32 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: chrl %r2, g
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i32
   %cond = icmp ne i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
   %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: ch %r2, 0([[REG]])
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@h, align 1
   %src2 = sext i16 %val to i32
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
   %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }
 
 ; Check the comparison can be reversed if that allows CHRL to be used.
 define i32 @f6(i32 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: chrl %r2, g
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src1 = sext i16 %val to i32
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src2, %src2
   br label %exit
 exit:
   %res = phi i32 [ %src2, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-37.ll

entry:
   %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
-  %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
+  %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
+  %res = add i32 %tmp, 1
   ret i32 %res
 }
 
 ; Check signed comparison.
 define i32 @f2(i32 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: clhrl
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
-  %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
+  %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
+  %res = add i32 %tmp, 1
   ret i32 %res
 }
 
 ; Check equality.
 define i32 @f3(i32 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp eq i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
-  %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
+  %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
+  %res = add i32 %tmp, 1
   ret i32 %res
 }
 
 ; Check inequality.
 define i32 @f4(i32 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i32
   %cond = icmp ne i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
-  %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
+  %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
+  %res = add i32 %tmp, 1
   ret i32 %res
 }
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: clrjl %r2, [[VAL]],
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@h, align 1
   %src2 = zext i16 %val to i32
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
-  %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
+  %tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
+  %res = add i32 %tmp, 1
   ret i32 %res
 }
 
 ; Check the comparison can be reversed if that allows CLHRL to be used.
 define i32 @f6(i32 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src1 = zext i16 %val to i32
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src2, %src2
   br label %exit
 exit:
-  %res = phi i32 [ %src2, %entry ], [ %mul, %mulb ]
+  %tmp = phi i32 [ %src2, %entry ], [ %mul, %mulb ]
+  %res = add i32 %tmp, 1
   ret i32 %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-38.ll

 ; Test 32-bit comparisons in which the second operand is a PC-relative
 ; variable.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 @g = global i32 1
 @h = global i32 1, align 2, section "foo"
 
 ; Check signed comparisons.
 define i32 @f1(i32 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: crl %r2, g
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %src2 = load i32 , i32 *@g
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
   %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }
 
 ; Check unsigned comparisons.
 define i32 @f2(i32 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK: clrl %r2, g
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %src2 = load i32 , i32 *@g
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
   %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }
 
 ; Check equality, which can use CRL or CLRL.
 define i32 @f3(i32 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: c{{l?}}rl %r2, g
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %src2 = load i32 , i32 *@g
   %cond = icmp eq i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
   %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }
 
 ; ...likewise inequality.
 define i32 @f4(i32 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: c{{l?}}rl %r2, g
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
 entry:
   %src2 = load i32 , i32 *@g
   %cond = icmp ne i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
   %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: c %r2, 0([[REG]])
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %src2 = load i32 , i32 *@h, align 2
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
   %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }
 
 ; Repeat f2 with an unaligned address.
 define i32 @f6(i32 %src1) {
 ; CHECK-LABEL: f6:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cl %r2, 0([[REG]])
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %src2 = load i32 , i32 *@h, align 2
   %cond = icmp ult i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src1, %src1
   br label %exit
 exit:
   %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }
 
 ; Check the comparison can be reversed if that allows CRL to be used.
 define i32 @f7(i32 %src2) {
 ; CHECK-LABEL: f7:
 ; CHECK: crl %r2, g
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %src1 = load i32 , i32 *@g
   %cond = icmp slt i32 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i32 %src2, %src2
   br label %exit
 exit:
   %res = phi i32 [ %src2, %entry ], [ %mul, %mulb ]
   ret i32 %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-39.ll

 ; Test 64-bit comparisons in which the second operand is sign-extended
 ; from a PC-relative i16.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 @g = global i16 1
 @h = global i16 1, align 1, section "foo"
 
 ; Check signed comparison.
 define i64 @f1(i64 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: cghrl %r2, g
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: cghrl %r2, g
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i64
   %cond = icmp eq i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: cghrl %r2, g
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = sext i16 %val to i64
   %cond = icmp ne i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: cgh %r2, 0([[REG]])
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@h, align 1
   %src2 = sext i16 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check the comparison can be reversed if that allows CGHRL to be used.
 define i64 @f6(i64 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: cghrl %r2, g
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src1 = sext i16 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src2, %src2
   br label %exit
 exit:
   %res = phi i64 [ %src2, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-40.ll

entry:
   %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
-  %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
+  %tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
+  %res = add i64 %tmp, 1
   ret i64 %res
 }
 
 ; Check signed comparison.
 define i64 @f2(i64 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK-NOT: clghrl
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
-  %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
+  %tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
+  %res = add i64 %tmp, 1
   ret i64 %res
 }
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i64
   %cond = icmp eq i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
-  %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
+  %tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
+  %res = add i64 %tmp, 1
   ret i64 %res
 }
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src2 = zext i16 %val to i64
   %cond = icmp ne i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
-  %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
+  %tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
+  %res = add i64 %tmp, 1
   ret i64 %res
 }
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: llgh [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: clgrjl %r2, [[VAL]],
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@h, align 1
   %src2 = zext i16 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
-  %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
+  %tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
+  %res = add i64 %tmp, 1
   ret i64 %res
 }
 
 ; Check the comparison can be reversed if that allows CLGHRL to be used.
 define i64 @f6(i64 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: jh {{\.L.*}}
 ; CHECK: br %r14
 entry:
   %val = load i16 , i16 *@g
   %src1 = zext i16 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src2, %src2
   br label %exit
 exit:
-  %res = phi i64 [ %src2, %entry ], [ %mul, %mulb ]
+  %tmp = phi i64 [ %src2, %entry ], [ %mul, %mulb ]
+  %res = add i64 %tmp, 1
   ret i64 %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-41.ll

 ; Test 64-bit comparisons in which the second operand is sign-extended
 ; from a PC-relative i32.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 @g = global i32 1
 @h = global i32 1, align 2, section "foo"
 
 ; Check signed comparison.
 define i64 @f1(i64 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: cgfrl %r2, g
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %val = load i32 , i32 *@g
   %src2 = sext i32 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: cgfrl %r2, g
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %val = load i32 , i32 *@g
   %src2 = sext i32 %val to i64
   %cond = icmp eq i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: cgfrl %r2, g
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
 entry:
   %val = load i32 , i32 *@g
   %src2 = sext i32 %val to i64
   %cond = icmp ne i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cgf %r2, 0([[REG]])
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %val = load i32 , i32 *@h, align 2
   %src2 = sext i32 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check the comparison can be reversed if that allows CGFRL to be used.
 define i64 @f6(i64 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: cgfrl %r2, g
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %val = load i32 , i32 *@g
   %src1 = sext i32 %val to i64
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src2, %src2
   br label %exit
 exit:
   %res = phi i64 [ %src2, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-42.ll

 ; Test 64-bit comparisons in which the second operand is zero-extended
 ; from a PC-relative i32.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 @g = global i32 1
 @h = global i32 1, align 2, section "foo"
 
 ; Check unsigned comparison.
 define i64 @f1(i64 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: clgfrl %r2, g
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %val = load i32 , i32 *@g
   %src2 = zext i32 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: clgfrl %r2, g
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %val = load i32 , i32 *@g
   %src2 = zext i32 %val to i64
   %cond = icmp eq i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: clgfrl %r2, g
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
 entry:
   %val = load i32 , i32 *@g
   %src2 = zext i32 %val to i64
   %cond = icmp ne i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: clgf %r2, 0([[REG]])
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %val = load i32 , i32 *@h, align 2
   %src2 = zext i32 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check the comparison can be reversed if that allows CLGFRL to be used.
 define i64 @f6(i64 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: clgfrl %r2, g
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %val = load i32 , i32 *@g
   %src1 = zext i32 %val to i64
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src2, %src2
   br label %exit
 exit:
   %res = phi i64 [ %src2, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-43.ll

 ; Test 64-bit comparisons in which the second operand is a PC-relative
 ; variable.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 @g = global i64 1
 @h = global i64 1, align 4, section "foo"
 
 ; Check signed comparisons.
 define i64 @f1(i64 %src1) {
 ; CHECK-LABEL: f1:
 ; CHECK: cgrl %r2, g
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %src2 = load i64 , i64 *@g
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check unsigned comparisons.
 define i64 @f2(i64 %src1) {
 ; CHECK-LABEL: f2:
 ; CHECK: clgrl %r2, g
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %src2 = load i64 , i64 *@g
   %cond = icmp ult i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check equality, which can use CRL or CLRL.
 define i64 @f3(i64 %src1) {
 ; CHECK-LABEL: f3:
 ; CHECK: c{{l?}}grl %r2, g
-; CHECK-NEXT: je
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %src2 = load i64 , i64 *@g
   %cond = icmp eq i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; ...likewise inequality.
 define i64 @f4(i64 %src1) {
 ; CHECK-LABEL: f4:
 ; CHECK: c{{l?}}grl %r2, g
-; CHECK-NEXT: jlh
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
 entry:
   %src2 = load i64 , i64 *@g
   %cond = icmp ne i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
 ; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cg %r2, 0([[REG]])
-; CHECK-NEXT: jl
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %src2 = load i64 , i64 *@h, align 4
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src1, %src1
   br label %exit
 exit:
   %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }
 
 ; Check the comparison can be reversed if that allows CGRL to be used.
 define i64 @f6(i64 %src2) {
 ; CHECK-LABEL: f6:
 ; CHECK: cgrl %r2, g
-; CHECK-NEXT: jh {{\.L.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %src1 = load i64 , i64 *@g
   %cond = icmp slt i64 %src1, %src2
   br i1 %cond, label %exit, label %mulb
 mulb:
   %mul = mul i64 %src2, %src2
   br label %exit
 exit:
   %res = phi i64 [ %src2, %entry ], [ %mul, %mulb ]
   ret i64 %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-44.ll

 ; Test that compares are omitted if CC already has the right value
 ; (z10 version).
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-integrated-as \
 ; RUN:   -verify-machineinstrs| FileCheck %s
 
 declare void @foo()
 
 ; Addition provides enough for equality comparisons with zero.  First teest
 ; the EQ case.
 define i32 @f1(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f1:
 ; CHECK: afi %r2, 1000000
-; CHECK-NEXT: je .L{{.*}}
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %res = add i32 %a, 1000000
   %cmp = icmp eq i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...and again with NE.
 define i32 @f2(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f2:
 ; CHECK: afi %r2, 1000000
-; CHECK-NEXT: jne .L{{.*}}
+; CHECK-NEXT: bner %r14
 ; CHECK: br %r14
 entry:
   %res = add i32 %a, 1000000
   %cmp = icmp ne i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; SLT requires a comparison.
 define i32 @f3(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f3:
 ; CHECK: afi %r2, 1000000
-; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
+; CHECK-NEXT: cibl %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %res = add i32 %a, 1000000
   %cmp = icmp slt i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...SLE too.
 define i32 @f4(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f4:
 ; CHECK: afi %r2, 1000000
-; CHECK-NEXT: cijle %r2, 0, .L{{.*}}
+; CHECK-NEXT: cible %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %res = add i32 %a, 1000000
   %cmp = icmp sle i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...SGT too.
 define i32 @f5(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f5:
 ; CHECK: afi %r2, 1000000
-; CHECK-NEXT: cijh %r2, 0, .L{{.*}}
+; CHECK-NEXT: cibh %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %res = add i32 %a, 1000000
   %cmp = icmp sgt i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...SGE too.
 define i32 @f6(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f6:
 ; CHECK: afi %r2, 1000000
-; CHECK-NEXT: cijhe %r2, 0, .L{{.*}}
+; CHECK-NEXT: cibhe %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %res = add i32 %a, 1000000
   %cmp = icmp sge i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; Subtraction also provides enough for equality comparisons with zero.
 define i32 @f7(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f7:
 ; CHECK: s %r2, 0(%r4)
-; CHECK-NEXT: jne .L{{.*}}
+; CHECK-NEXT: bner %r14
 ; CHECK: br %r14
 entry:
   %cur = load i32 , i32 *%dest
   %res = sub i32 %a, %cur
   %cmp = icmp ne i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...but not for ordered comparisons.
 define i32 @f8(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f8:
 ; CHECK: s %r2, 0(%r4)
-; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
+; CHECK-NEXT: cibl %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %cur = load i32 , i32 *%dest
   %res = sub i32 %a, %cur
   %cmp = icmp slt i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; Logic register-register instructions also provide enough for equality
 ; comparisons with zero.
 define i32 @f9(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f9:
 ; CHECK: nr %r2, %r3
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %res = and i32 %a, %b
   %cmp = icmp ne i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...but not for ordered comparisons.
 define i32 @f10(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f10:
 ; CHECK: nr %r2, %r3
-; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
+; CHECK-NEXT: cibl %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %res = and i32 %a, %b
   %cmp = icmp slt i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; Logic register-immediate instructions also provide enough for equality
 ; comparisons with zero if the immediate covers the whole register.
 define i32 @f11(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f11:
 ; CHECK: nilf %r2, 100000001
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %res = and i32 %a, 100000001
   %cmp = icmp ne i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; Partial logic register-immediate instructions do not provide simple
 ; zero results.
 define i32 @f12(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f12:
 ; CHECK: nill %r2, 65436
-; CHECK-NEXT: cijlh %r2, 0, .L{{.*}}
+; CHECK-NEXT: ciblh %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %res = and i32 %a, -100
   %cmp = icmp ne i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; SRA provides the same CC result as a comparison with zero.
 define i32 @f13(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f13:
 ; CHECK: sra %r2, 0(%r3)
-; CHECK-NEXT: je .L{{.*}}
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %res = ashr i32 %a, %b
   %cmp = icmp eq i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...and again with NE.
 define i32 @f14(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f14:
 ; CHECK: sra %r2, 0(%r3)
-; CHECK-NEXT: jlh .L{{.*}}
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
 entry:
   %res = ashr i32 %a, %b
   %cmp = icmp ne i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...and SLT.
 define i32 @f15(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f15:
 ; CHECK: sra %r2, 0(%r3)
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %res = ashr i32 %a, %b
   %cmp = icmp slt i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...and SLE.
 define i32 @f16(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f16:
 ; CHECK: sra %r2, 0(%r3)
-; CHECK-NEXT: jle .L{{.*}}
+; CHECK-NEXT: bler %r14
 ; CHECK: br %r14
 entry:
   %res = ashr i32 %a, %b
   %cmp = icmp sle i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...and SGT.
 define i32 @f17(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f17:
 ; CHECK: sra %r2, 0(%r3)
-; CHECK-NEXT: jh .L{{.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %res = ashr i32 %a, %b
   %cmp = icmp sgt i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...and SGE.
 define i32 @f18(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f18:
 ; CHECK: sra %r2, 0(%r3)
-; CHECK-NEXT: jhe .L{{.*}}
+; CHECK-NEXT: bher %r14
 ; CHECK: br %r14
 entry:
   %res = ashr i32 %a, %b
   %cmp = icmp sge i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; RISBG provides the same result as a comparison against zero.
 ; Test the EQ case.
 define i64 @f19(i64 %a, i64 %b, i64 *%dest) {
 ; CHECK-LABEL: f19:
 ; CHECK: risbg %r2, %r3, 0, 190, 0
-; CHECK-NEXT: je .L{{.*}}
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
 entry:
   %res = and i64 %b, -2
   %cmp = icmp eq i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 %b, i64 *%dest
   br label %exit
 
 exit:
   ret i64 %res
 }
 
 ; ...and the SLT case.
 define i64 @f20(i64 %a, i64 %b, i64 *%dest) {
 ; CHECK-LABEL: f20:
 ; CHECK: risbg %r2, %r3, 0, 190, 0
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %res = and i64 %b, -2
   %cmp = icmp slt i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 %b, i64 *%dest
   br label %exit
 
 exit:
   ret i64 %res
 }
 
 ; Test a case where the register we're testing is set by a non-CC-clobbering
 ; instruction.
 define i32 @f21(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f21:
 ; CHECK: afi %r2, 1000000
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %r2
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: cije %r2, 0, .L{{.*}}
+; CHECK-NEXT: cibe %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %add = add i32 %a, 1000000
   %res = call i32 asm "blah $0", "=r,0" (i32 %add)
   %cmp = icmp eq i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; ...and again with a CC-clobbering instruction.
 define i32 @f22(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f22:
 ; CHECK: afi %r2, 1000000
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %r2
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: cije %r2, 0, .L{{.*}}
+; CHECK-NEXT: cibe %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %add = add i32 %a, 1000000
   %res = call i32 asm "blah $0", "=r,0,~{cc}" (i32 %add)
   %cmp = icmp eq i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; Check that stores do not interfere.
 define i32 @f23(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) {
 ; CHECK-LABEL: f23:
 ; CHECK: afi %r2, 1000000
 ; CHECK-NEXT: st %r2, 0(%r4)
-; CHECK-NEXT: jne .L{{.*}}
+; CHECK-NEXT: bner %r14
 ; CHECK: br %r14
 entry:
   %res = add i32 %a, 1000000
   store i32 %res, i32 *%dest1
   %cmp = icmp ne i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:

 
 ; Check that inline asms don't interfere if they don't clobber CC.
 define void @f25(i32 %a, i32 *%ptr) {
 ; CHECK-LABEL: f25:
 ; CHECK: afi %r2, 1000000
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jne .L{{.*}}
+; CHECK-NEXT: bner %r14
 ; CHECK: br %r14
 entry:
   %add = add i32 %a, 1000000
   call void asm sideeffect "blah", "r"(i32 %add)
   %cmp = icmp ne i32 %add, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %add, i32 *%ptr
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...but do interfere if they do clobber CC.
 define void @f26(i32 %a, i32 *%ptr) {
 ; CHECK-LABEL: f26:
 ; CHECK: afi %r2, 1000000
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: cijlh %r2, 0, .L{{.*}}
+; CHECK-NEXT: ciblh %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %add = add i32 %a, 1000000
   call void asm sideeffect "blah", "r,~{cc}"(i32 %add)
   %cmp = icmp ne i32 %add, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %add, i32 *%ptr
   br label %exit
 
 exit:
   ret void
 }
 
 ; Test a case where CC is set based on a different register from the
 ; compare input.
 define i32 @f27(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) {
 ; CHECK-LABEL: f27:
 ; CHECK: afi %r2, 1000000
 ; CHECK-NEXT: sr %r3, %r2
 ; CHECK-NEXT: st %r3, 0(%r4)
-; CHECK-NEXT: cije %r2, 0, .L{{.*}}
+; CHECK-NEXT: cibe %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %add = add i32 %a, 1000000
   %sub = sub i32 %b, %add
   store i32 %sub, i32 *%dest1
   %cmp = icmp eq i32 %add, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %sub, i32 *%dest2
   br label %exit
 
 exit:
   ret i32 %add
 }
 
 ; Make sure that we don't confuse a base register for a destination.
 define void @f28(i64 %a, i64 *%dest) {
 ; CHECK-LABEL: f28:
 ; CHECK: xi 0(%r2), 15
-; CHECK: cgije %r2, 0, .L{{.*}}
+; CHECK: cgibe %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %ptr = inttoptr i64 %a to i8 *
   %val = load i8 , i8 *%ptr
   %xor = xor i8 %val, 15
   store i8 %xor, i8 *%ptr
   %cmp = icmp eq i64 %a, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 %a, i64 *%dest
   br label %exit
 
 exit:
   ret void
 }
 
 ; Test that L gets converted to LT where useful.
 define i32 @f29(i64 %base, i64 %index, i32 *%dest) {
 ; CHECK-LABEL: f29:
 ; CHECK: lt %r2, 0({{%r2,%r3|%r3,%r2}})
-; CHECK-NEXT: jle .L{{.*}}
+; CHECK-NEXT: bler %r14
 ; CHECK: br %r14
 entry:
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
   %res = load i32 , i32 *%ptr
   %cmp = icmp sle i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %res, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; Test that LY gets converted to LT where useful.
 define i32 @f30(i64 %base, i64 %index, i32 *%dest) {
 ; CHECK-LABEL: f30:
 ; CHECK: lt %r2, 100000({{%r2,%r3|%r3,%r2}})
-; CHECK-NEXT: jle .L{{.*}}
+; CHECK-NEXT: bler %r14
 ; CHECK: br %r14
 entry:
   %add1 = add i64 %base, %index
   %add2 = add i64 %add1, 100000
   %ptr = inttoptr i64 %add2 to i32 *
   %res = load i32 , i32 *%ptr
   %cmp = icmp sle i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %res, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; Test that LG gets converted to LTG where useful.
 define i64 @f31(i64 %base, i64 %index, i64 *%dest) {
 ; CHECK-LABEL: f31:
 ; CHECK: ltg %r2, 0({{%r2,%r3|%r3,%r2}})
-; CHECK-NEXT: jhe .L{{.*}}
+; CHECK-NEXT: bher %r14
 ; CHECK: br %r14
 entry:
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i64 *
   %res = load i64 , i64 *%ptr
   %cmp = icmp sge i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 %res, i64 *%dest
   br label %exit
 
 exit:
   ret i64 %res
 }
 
 ; Test that LGF gets converted to LTGF where useful.
 define i64 @f32(i64 %base, i64 %index, i64 *%dest) {
 ; CHECK-LABEL: f32:
 ; CHECK: ltgf %r2, 0({{%r2,%r3|%r3,%r2}})
-; CHECK-NEXT: jh .L{{.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
   %val = load i32 , i32 *%ptr
   %res = sext i32 %val to i64
   %cmp = icmp sgt i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 %res, i64 *%dest
   br label %exit
 
 exit:
   ret i64 %res
 }
 
 ; Test that LR gets converted to LTR where useful.
 define i32 @f33(i32 %dummy, i32 %val, i32 *%dest) {
 ; CHECK-LABEL: f33:
 ; CHECK: ltr %r2, %r3
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %r2
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   call void asm sideeffect "blah $0", "{r2}"(i32 %val)
   %cmp = icmp slt i32 %val, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %val, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %val
 }
 
 ; Test that LGR gets converted to LTGR where useful.
 define i64 @f34(i64 %dummy, i64 %val, i64 *%dest) {
 ; CHECK-LABEL: f34:
 ; CHECK: ltgr %r2, %r3
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %r2
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jh .L{{.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   call void asm sideeffect "blah $0", "{r2}"(i64 %val)
   %cmp = icmp sgt i64 %val, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 %val, i64 *%dest
   br label %exit
 
 exit:
   ret i64 %val
 }
 
 ; Test that LGFR gets converted to LTGFR where useful.
 define i64 @f35(i64 %dummy, i32 %val, i64 *%dest) {
 ; CHECK-LABEL: f35:
 ; CHECK: ltgfr %r2, %r3
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %r2
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jh .L{{.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %ext = sext i32 %val to i64
   call void asm sideeffect "blah $0", "{r2}"(i64 %ext)
   %cmp = icmp sgt i64 %ext, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 %ext, i64 *%dest
   br label %exit
 
 exit:
   ret i64 %ext
 }
 
 ; Test a case where it is the source rather than destination of LR that
 ; we need.
 define i32 @f36(i32 %val, i32 %dummy, i32 *%dest) {
 ; CHECK-LABEL: f36:
 ; CHECK: ltr %r3, %r2
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %r3
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   call void asm sideeffect "blah $0", "{r3}"(i32 %val)
   %cmp = icmp slt i32 %val, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %val, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %val
 }
 
 ; Test a case where it is the source rather than destination of LGR that
 ; we need.
 define i64 @f37(i64 %val, i64 %dummy, i64 *%dest) {
 ; CHECK-LABEL: f37:
 ; CHECK: ltgr %r3, %r2
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %r3
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   call void asm sideeffect "blah $0", "{r3}"(i64 %val)
   %cmp = icmp slt i64 %val, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 %val, i64 *%dest
   br label %exit
 
 exit:
   ret i64 %val
 }
 
 ; Test a case where it is the source rather than destination of LGFR that
 ; we need.
 define i32 @f38(i32 %val, i64 %dummy, i32 *%dest) {
 ; CHECK-LABEL: f38:
 ; CHECK: ltgfr %r3, %r2
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %r3
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jl .L{{.*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %ext = sext i32 %val to i64
   call void asm sideeffect "blah $0", "{r3}"(i64 %ext)
   %cmp = icmp slt i32 %val, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %val, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %val
 }
 
 ; Test f35 for in-register extensions.
 define i64 @f39(i64 %dummy, i64 %a, i64 *%dest) {
 ; CHECK-LABEL: f39:
 ; CHECK: ltgfr %r2, %r3
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %r2
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jh .L{{.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %val = trunc i64 %a to i32
   %ext = sext i32 %val to i64
   call void asm sideeffect "blah $0", "{r2}"(i64 %ext)
   %cmp = icmp sgt i64 %ext, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 %ext, i64 *%dest
   br label %exit
 
 exit:
   ret i64 %ext
 }
 
 ; ...and again with what InstCombine would produce for f40.
 define i64 @f40(i64 %dummy, i64 %a, i64 *%dest) {
 ; CHECK-LABEL: f40:
 ; CHECK: ltgfr %r2, %r3
 ; CHECK-NEXT: #APP
 ; CHECK-NEXT: blah %r2
 ; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: jh .L{{.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %shl = shl i64 %a, 32
   %ext = ashr i64 %shl, 32
   call void asm sideeffect "blah $0", "{r2}"(i64 %ext)
   %cmp = icmp sgt i64 %shl, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 %ext, i64 *%dest
   br label %exit
 
 exit:
   ret i64 %ext
 }
 
 ; Try a form of f7 in which the subtraction operands are compared directly.
 define i32 @f41(i32 %a, i32 %b, i32 *%dest) {
 ; CHECK-LABEL: f41:
 ; CHECK: s %r2, 0(%r4)
-; CHECK-NEXT: jne .L{{.*}}
+; CHECK-NEXT: bner %r14
 ; CHECK: br %r14
 entry:
   %cur = load i32 , i32 *%dest
   %res = sub i32 %a, %cur
   %cmp = icmp ne i32 %a, %cur
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 %b, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }
 
 ; A version of f32 that tests the unextended value.
 define i64 @f42(i64 %base, i64 %index, i64 *%dest) {
 ; CHECK-LABEL: f42:
 ; CHECK: ltgf %r2, 0({{%r2,%r3|%r3,%r2}})
-; CHECK-NEXT: jh .L{{.*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %add = add i64 %base, %index
   %ptr = inttoptr i64 %add to i32 *
   %val = load i32 , i32 *%ptr
   %res = sext i32 %val to i64
   %cmp = icmp sgt i32 %val, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 %res, i64 *%dest
   br label %exit
 
 exit:
   ret i64 %res
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-46.ll

 ; Test the use of TEST UNDER MASK for 32-bit operations.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
 
 @g = global i32 0
 
 ; Check the lowest useful TMLL value.
 define void @f1(i32 %a) {
 ; CHECK-LABEL: f1:
 ; CHECK: tmll %r2, 1
-; CHECK: je {{\.L.*}}
+; CHECK: ber %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 1
   %cmp = icmp eq i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the high end of the TMLL range.
 define void @f2(i32 %a) {
 ; CHECK-LABEL: f2:
 ; CHECK: tmll %r2, 65535
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 65535
   %cmp = icmp ne i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the lowest useful TMLH value, which is the next value up.
 define void @f3(i32 %a) {
 ; CHECK-LABEL: f3:
 ; CHECK: tmlh %r2, 1
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 65536
   %cmp = icmp ne i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g

 exit:
   ret void
 }
 
 ; Check the high end of the TMLH range.
 define void @f5(i32 %a) {
 ; CHECK-LABEL: f5:
 ; CHECK: tmlh %r2, 65535
-; CHECK: je {{\.L.*}}
+; CHECK: ber %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 4294901760
   %cmp = icmp eq i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for LT comparisons that are equivalent to
 ; an equality comparison with zero.
 define void @f6(i32 %a) {
 ; CHECK-LABEL: f6:
 ; CHECK: tmll %r2, 240
-; CHECK: je {{\.L.*}}
+; CHECK: ber %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 240
   %cmp = icmp slt i32 %and, 16
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again with LE.
 define void @f7(i32 %a) {
 ; CHECK-LABEL: f7:
 ; CHECK: tmll %r2, 240
-; CHECK: je {{\.L.*}}
+; CHECK: ber %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 240
   %cmp = icmp sle i32 %and, 15
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for GE comparisons that are equivalent to
 ; an inequality comparison with zero.
 define void @f8(i32 %a) {
 ; CHECK-LABEL: f8:
 ; CHECK: tmll %r2, 240
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 240
   %cmp = icmp uge i32 %and, 16
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again with GT.
 define void @f9(i32 %a) {
 ; CHECK-LABEL: f9:
 ; CHECK: tmll %r2, 240
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 240
   %cmp = icmp ugt i32 %and, 15
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for LT comparisons that effectively
 ; test whether the top bit is clear.
 define void @f10(i32 %a) {
 ; CHECK-LABEL: f10:
 ; CHECK: tmll %r2, 35
-; CHECK: jle {{\.L.*}}
+; CHECK: bler %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 35
   %cmp = icmp ult i32 %and, 8
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again with LE.
 define void @f11(i32 %a) {
 ; CHECK-LABEL: f11:
 ; CHECK: tmll %r2, 35
-; CHECK: jle {{\.L.*}}
+; CHECK: bler %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 35
   %cmp = icmp ule i32 %and, 31
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for GE comparisons that effectively test
 ; whether the top bit is set.
 define void @f12(i32 %a) {
 ; CHECK-LABEL: f12:
 ; CHECK: tmll %r2, 140
-; CHECK: jnle {{\.L.*}}
+; CHECK: bnler %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 140
   %cmp = icmp uge i32 %and, 128
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again for GT.
 define void @f13(i32 %a) {
 ; CHECK-LABEL: f13:
 ; CHECK: tmll %r2, 140
-; CHECK: jnle {{\.L.*}}
+; CHECK: bnler %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 140
   %cmp = icmp ugt i32 %and, 126
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for equality comparisons with the mask.
 define void @f14(i32 %a) {
 ; CHECK-LABEL: f14:
 ; CHECK: tmll %r2, 101
-; CHECK: jo {{\.L.*}}
+; CHECK: bor %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 101
   %cmp = icmp eq i32 %and, 101
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for inequality comparisons with the mask.
 define void @f15(i32 %a) {
 ; CHECK-LABEL: f15:
 ; CHECK: tmll %r2, 65519
-; CHECK: jno {{\.L.*}}
+; CHECK: bnor %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 65519
   %cmp = icmp ne i32 %and, 65519
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for LT comparisons that are equivalent
 ; to inequality comparisons with the mask.
 define void @f16(i32 %a) {
 ; CHECK-LABEL: f16:
 ; CHECK: tmll %r2, 130
-; CHECK: jno {{\.L.*}}
+; CHECK: bnor %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 130
   %cmp = icmp ult i32 %and, 129
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again with LE.
 define void @f17(i32 %a) {
 ; CHECK-LABEL: f17:
 ; CHECK: tmll %r2, 130
-; CHECK: jno {{\.L.*}}
+; CHECK: bnor %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 130
   %cmp = icmp ule i32 %and, 128
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for GE comparisons that are equivalent
 ; to equality comparisons with the mask.
 define void @f18(i32 %a) {
 ; CHECK-LABEL: f18:
 ; CHECK: tmll %r2, 194
-; CHECK: jo {{\.L.*}}
+; CHECK: bor %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 194
   %cmp = icmp uge i32 %and, 193
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; ...same again for GT.
 define void @f19(i32 %a) {
 ; CHECK-LABEL: f19:
 ; CHECK: tmll %r2, 194
-; CHECK: jo {{\.L.*}}
+; CHECK: bor %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 194
   %cmp = icmp ugt i32 %and, 192
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for equality comparisons for the low bit
 ; when the mask has two bits.
 define void @f20(i32 %a) {
 ; CHECK-LABEL: f20:
 ; CHECK: tmll %r2, 20
-; CHECK: jl {{\.L.*}}
+; CHECK: blr %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 20
   %cmp = icmp eq i32 %and, 4
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for inequality comparisons for the low bit
 ; when the mask has two bits.
 define void @f21(i32 %a) {
 ; CHECK-LABEL: f21:
 ; CHECK: tmll %r2, 20
-; CHECK: jnl {{\.L.*}}
+; CHECK: bnlr %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 20
   %cmp = icmp ne i32 %and, 4
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for equality comparisons for the high bit
 ; when the mask has two bits.
 define void @f22(i32 %a) {
 ; CHECK-LABEL: f22:
 ; CHECK: tmll %r2, 20
-; CHECK: jh {{\.L.*}}
+; CHECK: bhr %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 20
   %cmp = icmp eq i32 %and, 16
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can use TMLL for inequality comparisons for the high bit
 ; when the mask has two bits.
 define void @f23(i32 %a) {
 ; CHECK-LABEL: f23:
 ; CHECK: tmll %r2, 20
-; CHECK: jnh {{\.L.*}}
+; CHECK: bnhr %r14
 ; CHECK: br %r14
 entry:
   %and = and i32 %a, 20
   %cmp = icmp ne i32 %and, 16
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can fold an SHL into a TMxx mask.
 define void @f24(i32 %a) {
 ; CHECK-LABEL: f24:
 ; CHECK: tmll %r2, 255
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %shl = shl i32 %a, 12
   %and = and i32 %shl, 1044480
   %cmp = icmp ne i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can fold an SHR into a TMxx mask.
 define void @f25(i32 %a) {
 ; CHECK-LABEL: f25:
 ; CHECK: tmlh %r2, 512
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %shr = lshr i32 %a, 25
   %and = and i32 %shr, 1
   %cmp = icmp ne i32 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-47.ll

 ; Test the use of TEST UNDER MASK for 64-bit operations.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
 
 @g = global i32 0
 
 ; Check the lowest useful TMLL value.
 define void @f1(i64 %a) {
 ; CHECK-LABEL: f1:
 ; CHECK: tmll %r2, 1
-; CHECK: je {{\.L.*}}
+; CHECK: ber %r14
 ; CHECK: br %r14
 entry:
   %and = and i64 %a, 1
   %cmp = icmp eq i64 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the high end of the TMLL range.
 define void @f2(i64 %a) {
 ; CHECK-LABEL: f2:
 ; CHECK: tmll %r2, 65535
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %and = and i64 %a, 65535
   %cmp = icmp ne i64 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the lowest useful TMLH value, which is the next value up.
 define void @f3(i64 %a) {
 ; CHECK-LABEL: f3:
 ; CHECK: tmlh %r2, 1
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %and = and i64 %a, 65536
   %cmp = icmp ne i64 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g

 exit:
   ret void
 }
 
 ; Check the high end of the TMLH range.
 define void @f5(i64 %a) {
 ; CHECK-LABEL: f5:
 ; CHECK: tmlh %r2, 65535
-; CHECK: je {{\.L.*}}
+; CHECK: ber %r14
 ; CHECK: br %r14
 entry:
   %and = and i64 %a, 4294901760
   %cmp = icmp eq i64 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the lowest useful TMHL value.
 define void @f6(i64 %a) {
 ; CHECK-LABEL: f6:
 ; CHECK: tmhl %r2, 1
-; CHECK: je {{\.L.*}}
+; CHECK: ber %r14
 ; CHECK: br %r14
 entry:
   %and = and i64 %a, 4294967296
   %cmp = icmp eq i64 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g

 exit:
   ret void
 }
 
 ; Check the high end of the TMHL range.
 define void @f8(i64 %a) {
 ; CHECK-LABEL: f8:
 ; CHECK: tmhl %r2, 65535
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %and = and i64 %a, 281470681743360
   %cmp = icmp ne i64 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the lowest useful TMHH value.
 define void @f9(i64 %a) {
 ; CHECK-LABEL: f9:
 ; CHECK: tmhh %r2, 1
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %and = and i64 %a, 281474976710656
   %cmp = icmp ne i64 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the high end of the TMHH range.
 define void @f10(i64 %a) {
 ; CHECK-LABEL: f10:
 ; CHECK: tmhh %r2, 65535
-; CHECK: je {{\.L.*}}
+; CHECK: ber %r14
 ; CHECK: br %r14
 entry:
   %and = and i64 %a, 18446462598732840960
   %cmp = icmp eq i64 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can fold an SHL into a TMxx mask.
 define void @f11(i64 %a) {
 ; CHECK-LABEL: f11:
 ; CHECK: tmhl %r2, 32768
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %shl = shl i64 %a, 1
   %and = and i64 %shl, 281474976710656
   %cmp = icmp ne i64 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check that we can fold an SHR into a TMxx mask.
 define void @f12(i64 %a) {
 ; CHECK-LABEL: f12:
 ; CHECK: tmhh %r2, 256
-; CHECK: jne {{\.L.*}}
+; CHECK: bner %r14
 ; CHECK: br %r14
 entry:
   %shr = lshr i64 %a, 56
   %and = and i64 %shr, 1
   %cmp = icmp ne i64 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check a case where TMHH can be used to implement a ult comparison.
 define void @f13(i64 %a) {
 ; CHECK-LABEL: f13:
 ; CHECK: tmhh %r2, 49152
-; CHECK: jno {{\.L.*}}
+; CHECK: bnor %r14
 ; CHECK: br %r14
 entry:
   %cmp = icmp ult i64 %a, 13835058055282163712
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; And again with ule.
 define void @f14(i64 %a) {
 ; CHECK-LABEL: f14:
 ; CHECK: tmhh %r2, 49152
-; CHECK: jno {{\.L.*}}
+; CHECK: bnor %r14
 ; CHECK: br %r14
 entry:
   %cmp = icmp ule i64 %a, 13835058055282163711
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; And again with ugt.
 define void @f15(i64 %a) {
 ; CHECK-LABEL: f15:
 ; CHECK: tmhh %r2, 49152
-; CHECK: jo {{\.L.*}}
+; CHECK: bor %r14
 ; CHECK: br %r14
 entry:
   %cmp = icmp ugt i64 %a, 13835058055282163711
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 ; And again with uge.
 define void @f16(i64 %a) {
 ; CHECK-LABEL: f16:
 ; CHECK: tmhh %r2, 49152
-; CHECK: jo {{\.L.*}}
+; CHECK: bor %r14
 ; CHECK: br %r14
 entry:
   %cmp = icmp uge i64 %a, 13835058055282163712
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit

 exit:
   ret void
 }
 
 ; Check that we don't use TMHH just to test the top bit.
 define void @f18(i64 %a) {
 ; CHECK-LABEL: f18:
 ; CHECK-NOT: tmhh
-; CHECK: cgijhe %r2, 0,
+; CHECK: cgibhe %r2, 0, 0(%r14)
 ; CHECK: br %r14
 entry:
   %cmp = icmp ult i64 %a, 9223372036854775808
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }

llvm/trunk/test/CodeGen/SystemZ/int-cmp-48.ll

 ; Test the use of TM and TMY.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
 
 @g = global i32 0
 
 ; Check a simple branching use of TM.
 define void @f1(i8 *%src) {
 ; CHECK-LABEL: f1:
 ; CHECK: tm 0(%r2), 1
-; CHECK: je {{\.L.*}}
+; CHECK: ber %r14
 ; CHECK: br %r14
 entry:
   %byte = load i8 , i8 *%src
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 1, i32 *@g
   br label %exit
 
 exit:
   ret void
 }
 
 
 ; Check that we do not fold across an aliasing store.
 define void @f2(i8 *%src) {
 ; CHECK-LABEL: f2:
 ; CHECK: llc [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: tmll [[REG]], 1
-; CHECK: je {{\.L.*}}
+; CHECK: ber %r14
 ; CHECK: br %r14
 entry:
   %byte = load i8 , i8 *%src
   store i8 0, i8 *%src
   %and = and i8 %byte, 1
   %cmp = icmp eq i8 %and, 0
   br i1 %cmp, label %exit, label %store
 

llvm/trunk/test/CodeGen/SystemZ/memchr-01.ll

 ; Test memchr using SRST, with a weird but usable prototype.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs | FileCheck %s
 
 declare i8 *@memchr(i8 *%src, i16 %char, i32 %len)
 
 ; Test a simple forwarded call.
 define i8 *@f1(i8 *%src, i16 %char, i32 %len) {
 ; CHECK-LABEL: f1:
 ; CHECK-DAG: lgr [[REG:%r[1-5]]], %r2
 ; CHECK-DAG: algfr %r2, %r4
 ; CHECK-DAG: llcr %r0, %r3
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: srst %r2, [[REG]]
 ; CHECK-NEXT: jo [[LABEL]]
-; CHECK: jl {{\.L.*}}
+; CHECK: blr %r14
 ; CHECK: lghi %r2, 0
 ; CHECK: br %r14
   %res = call i8 *@memchr(i8 *%src, i16 %char, i32 %len)
   ret i8 *%res
 }

llvm/trunk/test/CodeGen/SystemZ/memchr-02.ll

 ; Test memchr using SRST, with the correct prototype.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -no-integrated-as | FileCheck %s
 
 declare i8 *@memchr(i8 *%src, i32 %char, i64 %len)
 
 ; Test a simple forwarded call.
 define i8 *@f1(i64 %len, i8 *%src, i32 %char) {
 ; CHECK-LABEL: f1:
 ; CHECK-DAG: agr %r2, %r3
 ; CHECK-DAG: llcr %r0, %r4
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: srst %r2, %r3
 ; CHECK-NEXT: jo [[LABEL]]
-; CHECK: jl {{\.L.*}}
+; CHECK: blr %r14
 ; CHECK: lghi %r2, 0
 ; CHECK: br %r14
   %res = call i8 *@memchr(i8 *%src, i32 %char, i64 %len)
   ret i8 *%res
 }
 
 ; Test a doubled call with no use of %r0 in between.  There should be a
 ; single load of %r0.

llvm/trunk/test/CodeGen/SystemZ/memcmp-01.ll

; CHECK: br %r14
   %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 2)
   ret i32 %res
 }
 
 ; Check a case where the result is tested for equality.
 define void @f3(i8 *%src1, i8 *%src2, i32 *%dest) {
 ; CHECK-LABEL: f3:
 ; CHECK: clc 0(3,%r2), 0(%r3)
-; CHECK-NEXT: je {{\..*}}
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 3)
   %cmp = icmp eq i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 0, i32 *%dest
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check a case where the result is tested for inequality.
 define void @f4(i8 *%src1, i8 *%src2, i32 *%dest) {
 ; CHECK-LABEL: f4:
 ; CHECK: clc 0(4,%r2), 0(%r3)
-; CHECK-NEXT: jlh {{\..*}}
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
 entry:
   %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 4)
   %cmp = icmp ne i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 0, i32 *%dest
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check a case where the result is tested via slt.
 define void @f5(i8 *%src1, i8 *%src2, i32 *%dest) {
 ; CHECK-LABEL: f5:
 ; CHECK: clc 0(5,%r2), 0(%r3)
-; CHECK-NEXT: jl {{\..*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 5)
   %cmp = icmp slt i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 0, i32 *%dest
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check a case where the result is tested for sgt.
 define void @f6(i8 *%src1, i8 *%src2, i32 *%dest) {
 ; CHECK-LABEL: f6:
 ; CHECK: clc 0(6,%r2), 0(%r3)
-; CHECK-NEXT: jh {{\..*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 6)
   %cmp = icmp sgt i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 0, i32 *%dest
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the upper end of the CLC range.  Here the result is used both as
 ; an integer and for branching.
 define i32 @f7(i8 *%src1, i8 *%src2, i32 *%dest) {
 ; CHECK-LABEL: f7:
 ; CHECK: clc 0(256,%r2), 0(%r3)
 ; CHECK: ipm [[REG:%r[0-5]]]
 ; CHECK: srl [[REG]], 28
 ; CHECK: rll %r2, [[REG]], 31
-; CHECK: jl {{.L*}}
+; CHECK: blr %r14
 ; CHECK: br %r14
 entry:
   %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 256)
   %cmp = icmp slt i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 0, i32 *%dest

 
 ; Test a comparison of 258 bytes in which the CC result can be used directly.
 define void @f9(i8 *%src1, i8 *%src2, i32 *%dest) {
 ; CHECK-LABEL: f9:
 ; CHECK: clc 0(256,%r2), 0(%r3)
 ; CHECK: jlh [[LABEL:\..*]]
 ; CHECK: clc 256(1,%r2), 256(%r3)
 ; CHECK: [[LABEL]]:
-; CHECK-NEXT: jl .L
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 257)
   %cmp = icmp slt i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 0, i32 *%dest

llvm/trunk/test/CodeGen/SystemZ/memcmp-02.ll

; CHECK: br %r14
   %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 2)
   ret i64 %res
 }
 
 ; Check a case where the result is tested for equality.
 define void @f3(i8 *%src1, i8 *%src2, i64 *%dest) {
 ; CHECK-LABEL: f3:
 ; CHECK: clc 0(3,%r2), 0(%r3)
-; CHECK-NEXT: je {{\..*}}
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 3)
   %cmp = icmp eq i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 0, i64 *%dest
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check a case where the result is tested for inequality.
 define void @f4(i8 *%src1, i8 *%src2, i64 *%dest) {
 ; CHECK-LABEL: f4:
 ; CHECK: clc 0(4,%r2), 0(%r3)
-; CHECK-NEXT: jlh {{\..*}}
+; CHECK-NEXT: blhr %r14
 ; CHECK: br %r14
 entry:
   %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 4)
   %cmp = icmp ne i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 0, i64 *%dest
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check a case where the result is tested via slt.
 define void @f5(i8 *%src1, i8 *%src2, i64 *%dest) {
 ; CHECK-LABEL: f5:
 ; CHECK: clc 0(5,%r2), 0(%r3)
-; CHECK-NEXT: jl {{\..*}}
+; CHECK-NEXT: blr %r14
 ; CHECK: br %r14
 entry:
   %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 5)
   %cmp = icmp slt i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 0, i64 *%dest
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check a case where the result is tested for sgt.
 define void @f6(i8 *%src1, i8 *%src2, i64 *%dest) {
 ; CHECK-LABEL: f6:
 ; CHECK: clc 0(6,%r2), 0(%r3)
-; CHECK-NEXT: jh {{\..*}}
+; CHECK-NEXT: bhr %r14
 ; CHECK: br %r14
 entry:
   %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 6)
   %cmp = icmp sgt i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 0, i64 *%dest
   br label %exit
 
 exit:
   ret void
 }
 
 ; Check the upper end of the CLC range.  Here the result is used both as
 ; an integer and for branching.
 define i64 @f7(i8 *%src1, i8 *%src2, i64 *%dest) {
 ; CHECK-LABEL: f7:
 ; CHECK: clc 0(256,%r2), 0(%r3)
 ; CHECK: ipm [[REG:%r[0-5]]]
 ; CHECK: srl [[REG]], 28
 ; CHECK: rll [[REG]], [[REG]], 31
 ; CHECK: lgfr %r2, [[REG]]
-; CHECK: jl {{.L*}}
+; CHECK: blr %r14
 ; CHECK: br %r14
 entry:
   %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 256)
   %cmp = icmp slt i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 0, i64 *%dest

llvm/trunk/test/CodeGen/SystemZ/strcmp-01.ll

 ; Check a case where the result is tested for equality.
 define void @f2(i8 *%src1, i8 *%src2, i32 *%dest) {
 ; CHECK-LABEL: f2:
 ; CHECK: lhi %r0, 0
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: clst %r2, %r3
 ; CHECK-NEXT: jo [[LABEL]]
 ; CHECK-NEXT: BB#{{[0-9]+}}
-; CHECK-NEXT: je {{\.L.*}}
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %res = call i32 @strcmp(i8 *%src1, i8 *%src2)
   %cmp = icmp eq i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 0, i32 *%dest
   br label %exit

 ; CHECK: lhi %r0, 0
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: clst %r2, %r3
 ; CHECK-NEXT: jo [[LABEL]]
 ; CHECK-NEXT: BB#{{[0-9]+}}
 ; CHECK-NEXT: ipm [[REG:%r[0-5]]]
 ; CHECK: srl [[REG]], 28
 ; CHECK: rll %r2, [[REG]], 31
-; CHECK: jl {{\.L*}}
+; CHECK: blr %r14
 ; CHECK: br %r14
 entry:
   %res = call i32 @strcmp(i8 *%src1, i8 *%src2)
   %cmp = icmp slt i32 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i32 0, i32 *%dest
   br label %exit
 
 exit:
   ret i32 %res
 }

llvm/trunk/test/CodeGen/SystemZ/strcmp-02.ll

 ; Check a case where the result is tested for equality.
 define void @f2(i8 *%src1, i8 *%src2, i64 *%dest) {
 ; CHECK-LABEL: f2:
 ; CHECK: lhi %r0, 0
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: clst %r2, %r3
 ; CHECK-NEXT: jo [[LABEL]]
 ; CHECK-NEXT: BB#{{[0-9]+}}
-; CHECK-NEXT: je {{\.L.*}}
+; CHECK-NEXT: ber %r14
 ; CHECK: br %r14
   %res = call i64 @strcmp(i8 *%src1, i8 *%src2)
   %cmp = icmp eq i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 0, i64 *%dest
   br label %exit

 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: clst %r2, %r3
 ; CHECK-NEXT: jo [[LABEL]]
 ; CHECK-NEXT: BB#{{[0-9]+}}
 ; CHECK-NEXT: ipm [[REG:%r[0-5]]]
 ; CHECK: srl [[REG]], 28
 ; CHECK: rll [[REG]], [[REG]], 31
 ; CHECK: lgfr %r2, [[REG]]
-; CHECK: jl {{\.L*}}
+; CHECK: blr %r14
 ; CHECK: br %r14
 entry:
   %res = call i64 @strcmp(i8 *%src1, i8 *%src2)
   %cmp = icmp slt i64 %res, 0
   br i1 %cmp, label %exit, label %store
 
 store:
   store i64 0, i64 *%dest
   br label %exit
 
 exit:
   ret i64 %res
 }

llvm/trunk/test/CodeGen/SystemZ/vec-intrinsics.ll

; CHECK: br %r14
   store i32 %cc, i32 *%ccptr
   ret <16 x i8> %res
 }
 
 ; VPKSHS, storing to %ptr if all values were saturated.
 define <16 x i8> @test_vpkshs_all_store(<8 x i16> %a, <8 x i16> %b, i32 *%ptr) {
 ; CHECK-LABEL: test_vpkshs_all_store:
 ; CHECK: vpkshs %v24, %v24, %v26
-; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK-NEXT: {{bnor|bler}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16> %a, <8 x i16> %b)
   %res = extractvalue {<16 x i8>, i32} %call, 0
   %cc = extractvalue {<16 x i8>, i32} %call, 1
   %cmp = icmp uge i32 %cc, 3
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   store i32 %cc, i32 *%ccptr
   ret <8 x i16> %res
 }
 
 ; VPKSFS, storing to %ptr if any values were saturated.
 define <8 x i16> @test_vpksfs_any_store(<4 x i32> %a, <4 x i32> %b, i32 *%ptr) {
 ; CHECK-LABEL: test_vpksfs_any_store:
 ; CHECK: vpksfs %v24, %v24, %v26
-; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK-NEXT: {{bher|ber}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b)
   %res = extractvalue {<8 x i16>, i32} %call, 0
   %cc = extractvalue {<8 x i16>, i32} %call, 1
   %cmp = icmp ugt i32 %cc, 0
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   ret <4 x i32> %res
 }
 
 ; VPKSGS, storing to %ptr if no elements were saturated
 define <4 x i32> @test_vpksgs_none_store(<2 x i64> %a, <2 x i64> %b,
                                          i32 *%ptr) {
 ; CHECK-LABEL: test_vpksgs_none_store:
 ; CHECK: vpksgs %v24, %v24, %v26
-; CHECK-NEXT: {{jnhe|jne}} {{\.L*}}
+; CHECK-NEXT: {{bnher|bner}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> %a, <2 x i64> %b)
   %res = extractvalue {<4 x i32>, i32} %call, 0
   %cc = extractvalue {<4 x i32>, i32} %call, 1
   %cmp = icmp sle i32 %cc, 0
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   ret <16 x i8> %res
 }
 
 ; VPKLSHS, storing to %ptr if all values were saturated.
 define <16 x i8> @test_vpklshs_all_store(<8 x i16> %a, <8 x i16> %b,
                                          i32 *%ptr) {
 ; CHECK-LABEL: test_vpklshs_all_store:
 ; CHECK: vpklshs %v24, %v24, %v26
-; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK-NEXT: {{bnor|bler}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16> %a, <8 x i16> %b)
   %res = extractvalue {<16 x i8>, i32} %call, 0
   %cc = extractvalue {<16 x i8>, i32} %call, 1
   %cmp = icmp eq i32 %cc, 3
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   ret <8 x i16> %res
 }
 
 ; VPKLSFS, storing to %ptr if any values were saturated.
 define <8 x i16> @test_vpklsfs_any_store(<4 x i32> %a, <4 x i32> %b,
                                          i32 *%ptr) {
 ; CHECK-LABEL: test_vpklsfs_any_store:
 ; CHECK: vpklsfs %v24, %v24, %v26
-; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK-NEXT: {{bher|ber}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> %a, <4 x i32> %b)
   %res = extractvalue {<8 x i16>, i32} %call, 0
   %cc = extractvalue {<8 x i16>, i32} %call, 1
   %cmp = icmp ne i32 %cc, 0
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   ret <4 x i32> %res
 }
 
 ; VPKLSGS, storing to %ptr if no elements were saturated
 define <4 x i32> @test_vpklsgs_none_store(<2 x i64> %a, <2 x i64> %b,
                                           i32 *%ptr) {
 ; CHECK-LABEL: test_vpklsgs_none_store:
 ; CHECK: vpklsgs %v24, %v24, %v26
-; CHECK-NEXT: {{jnhe|jne}} {{\.L*}}
+; CHECK-NEXT: {{bnher|bner}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> %a, <2 x i64> %b)
   %res = extractvalue {<4 x i32>, i32} %call, 0
   %cc = extractvalue {<4 x i32>, i32} %call, 1
   %cmp = icmp eq i32 %cc, 0
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   ret i32 %res
 }
 
 ; VTM, storing to %ptr if all bits are set.
 define void @test_vtm_all_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) {
 ; CHECK-LABEL: test_vtm_all_store:
 ; CHECK-NOT: %r
 ; CHECK: vtm %v24, %v26
-; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK-NEXT: {{bnor|bler}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %res = call i32 @llvm.s390.vtm(<16 x i8> %a, <16 x i8> %b)
   %cmp = icmp sge i32 %res, 3
   br i1 %cmp, label %store, label %exit
 
 store:
   store i32 0, i32 *%ptr
; CHECK: br %r14
   ret i32 %ext
 }
 
 ; VCEQBS, storing to %ptr if any elements are equal.
 define <16 x i8> @test_vceqbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) {
 ; CHECK-LABEL: test_vceqbs_any_store:
 ; CHECK-NOT: %r
 ; CHECK: vceqbs %v24, %v24, %v26
-; CHECK-NEXT: {{jo|jnle}} {{\.L*}}
+; CHECK-NEXT: {{bor|bnler}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b)
   %res = extractvalue {<16 x i8>, i32} %call, 0
   %cc = extractvalue {<16 x i8>, i32} %call, 1
   %cmp = icmp ule i32 %cc, 2
   br i1 %cmp, label %store, label %exit
 

 }
 
 ; VCEQHS, storing to %ptr if not all elements are equal.
 define <8 x i16> @test_vceqhs_notall_store(<8 x i16> %a, <8 x i16> %b,
                                            i32 *%ptr) {
 ; CHECK-LABEL: test_vceqhs_notall_store:
 ; CHECK-NOT: %r
 ; CHECK: vceqhs %v24, %v24, %v26
-; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK-NEXT: {{bher|ber}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b)
   %res = extractvalue {<8 x i16>, i32} %call, 0
   %cc = extractvalue {<8 x i16>, i32} %call, 1
   %cmp = icmp ugt i32 %cc, 0
   br i1 %cmp, label %store, label %exit
 

 }
 
 ; VCEQFS, storing to %ptr if no elements are equal.
 define <4 x i32> @test_vceqfs_none_store(<4 x i32> %a, <4 x i32> %b,
                                          i32 *%ptr) {
 ; CHECK-LABEL: test_vceqfs_none_store:
 ; CHECK-NOT: %r
 ; CHECK: vceqfs %v24, %v24, %v26
-; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK-NEXT: {{bnor|bler}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b)
   %res = extractvalue {<4 x i32>, i32} %call, 0
   %cc = extractvalue {<4 x i32>, i32} %call, 1
   %cmp = icmp uge i32 %cc, 3
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   ret i32 %ext
 }
 
 ; VCEQGS, storing to %ptr if all elements are equal.
 define <2 x i64> @test_vceqgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) {
 ; CHECK-LABEL: test_vceqgs_all_store:
 ; CHECK-NOT: %r
 ; CHECK: vceqgs %v24, %v24, %v26
-; CHECK-NEXT: {{jnhe|jne}} {{\.L*}}
+; CHECK-NEXT: {{bnher|bner}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b)
   %res = extractvalue {<2 x i64>, i32} %call, 0
   %cc = extractvalue {<2 x i64>, i32} %call, 1
   %cmp = icmp sle i32 %cc, 0
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   ret i32 %ext
 }
 
 ; VCHBS, storing to %ptr if any elements are higher.
 define <16 x i8> @test_vchbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) {
 ; CHECK-LABEL: test_vchbs_any_store:
 ; CHECK-NOT: %r
 ; CHECK: vchbs %v24, %v24, %v26
-; CHECK-NEXT: {{jo|jnle}} {{\.L*}}
+; CHECK-NEXT: {{bor|bnler}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b)
   %res = extractvalue {<16 x i8>, i32} %call, 0
   %cc = extractvalue {<16 x i8>, i32} %call, 1
   %cmp = icmp ule i32 %cc, 2
   br i1 %cmp, label %store, label %exit
 

 }
 
 ; VCHHS, storing to %ptr if not all elements are higher.
 define <8 x i16> @test_vchhs_notall_store(<8 x i16> %a, <8 x i16> %b,
                                           i32 *%ptr) {
 ; CHECK-LABEL: test_vchhs_notall_store:
 ; CHECK-NOT: %r
 ; CHECK: vchhs %v24, %v24, %v26
-; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK-NEXT: {{bher|ber}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b)
   %res = extractvalue {<8 x i16>, i32} %call, 0
   %cc = extractvalue {<8 x i16>, i32} %call, 1
   %cmp = icmp ugt i32 %cc, 0
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   ret i32 %ext
 }
 
 ; VCHFS, storing to %ptr if no elements are higher.
 define <4 x i32> @test_vchfs_none_store(<4 x i32> %a, <4 x i32> %b, i32 *%ptr) {
 ; CHECK-LABEL: test_vchfs_none_store:
 ; CHECK-NOT: %r
 ; CHECK: vchfs %v24, %v24, %v26
-; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK-NEXT: {{bnor|bler}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b)
   %res = extractvalue {<4 x i32>, i32} %call, 0
   %cc = extractvalue {<4 x i32>, i32} %call, 1
   %cmp = icmp uge i32 %cc, 3
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   ret i32 %ext
 }
 
 ; VCHGS, storing to %ptr if all elements are higher.
 define <2 x i64> @test_vchgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) {
 ; CHECK-LABEL: test_vchgs_all_store:
 ; CHECK-NOT: %r
 ; CHECK: vchgs %v24, %v24, %v26
-; CHECK-NEXT: {{jnhe|jne}} {{\.L*}}
+; CHECK-NEXT: {{bnher|bner}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b)
   %res = extractvalue {<2 x i64>, i32} %call, 0
   %cc = extractvalue {<2 x i64>, i32} %call, 1
   %cmp = icmp sle i32 %cc, 0
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   ret i32 %ext
 }
 
 ; VCHLBS, storing to %ptr if any elements are higher.
 define <16 x i8> @test_vchlbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) {
 ; CHECK-LABEL: test_vchlbs_any_store:
 ; CHECK-NOT: %r
 ; CHECK: vchlbs %v24, %v24, %v26
-; CHECK-NEXT: {{jo|jnle}} {{\.L*}}
+; CHECK-NEXT: {{bor|bnler}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b)
   %res = extractvalue {<16 x i8>, i32} %call, 0
   %cc = extractvalue {<16 x i8>, i32} %call, 1
   %cmp = icmp sle i32 %cc, 2
   br i1 %cmp, label %store, label %exit
 

 }
 
 ; VCHLHS, storing to %ptr if not all elements are higher.
 define <8 x i16> @test_vchlhs_notall_store(<8 x i16> %a, <8 x i16> %b,
                                            i32 *%ptr) {
 ; CHECK-LABEL: test_vchlhs_notall_store:
 ; CHECK-NOT: %r
 ; CHECK: vchlhs %v24, %v24, %v26
-; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK-NEXT: {{bher|ber}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b)
   %res = extractvalue {<8 x i16>, i32} %call, 0
   %cc = extractvalue {<8 x i16>, i32} %call, 1
   %cmp = icmp sgt i32 %cc, 0
   br i1 %cmp, label %store, label %exit
 

 }
 
 ; VCHLFS, storing to %ptr if no elements are higher.
 define <4 x i32> @test_vchlfs_none_store(<4 x i32> %a, <4 x i32> %b,
                                          i32 *%ptr) {
 ; CHECK-LABEL: test_vchlfs_none_store:
 ; CHECK-NOT: %r
 ; CHECK: vchlfs %v24, %v24, %v26
-; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK-NEXT: {{bnor|bler}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b)
   %res = extractvalue {<4 x i32>, i32} %call, 0
   %cc = extractvalue {<4 x i32>, i32} %call, 1
   %cmp = icmp sge i32 %cc, 3
   br i1 %cmp, label %store, label %exit
 
; CHECK: br %r14
   ret i32 %ext
 }
 
 ; VCHLGS, storing to %ptr if all elements are higher.
 define <2 x i64> @test_vchlgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) {
 ; CHECK-LABEL: test_vchlgs_all_store:
 ; CHECK-NOT: %r
 ; CHECK: vchlgs %v24, %v24, %v26
-; CHECK-NEXT: {{jnhe|jne}} {{\.L*}}
+; CHECK-NEXT: {{bnher|bner}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b)
   %res = extractvalue {<2 x i64>, i32} %call, 0
   %cc = extractvalue {<2 x i64>, i32} %call, 1
   %cmp = icmp ule i32 %cc, 0
   br i1 %cmp, label %store, label %exit
 

 }
 
 ; VFCEDBS, storing to %ptr if any elements are equal.
 define <2 x i64> @test_vfcedbs_any_store(<2 x double> %a, <2 x double> %b,
                                          i32 *%ptr) {
 ; CHECK-LABEL: test_vfcedbs_any_store:
 ; CHECK-NOT: %r
 ; CHECK: vfcedbs %v24, %v24, %v26
-; CHECK-NEXT: {{jo|jnle}} {{\.L*}}
+; CHECK-NEXT: {{bor|bnler}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a,
                                                    <2 x double> %b)
   %res = extractvalue {<2 x i64>, i32} %call, 0
   %cc = extractvalue {<2 x i64>, i32} %call, 1
   %cmp = icmp ule i32 %cc, 2
   br i1 %cmp, label %store, label %exit

 }
 
 ; VFCHDBS, storing to %ptr if not all elements are higher.
 define <2 x i64> @test_vfchdbs_notall_store(<2 x double> %a, <2 x double> %b,
                                             i32 *%ptr) {
 ; CHECK-LABEL: test_vfchdbs_notall_store:
 ; CHECK-NOT: %r
 ; CHECK: vfchdbs %v24, %v24, %v26
-; CHECK-NEXT: {{jhe|je}} {{\.L*}}
+; CHECK-NEXT: {{bher|ber}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a,
                                                    <2 x double> %b)
   %res = extractvalue {<2 x i64>, i32} %call, 0
   %cc = extractvalue {<2 x i64>, i32} %call, 1
   %cmp = icmp ugt i32 %cc, 0
   br i1 %cmp, label %store, label %exit

 }
 
 ; VFCHEDBS, storing to %ptr if neither element is higher or equal.
 define <2 x i64> @test_vfchedbs_none_store(<2 x double> %a, <2 x double> %b,
                                            i32 *%ptr) {
 ; CHECK-LABEL: test_vfchedbs_none_store:
 ; CHECK-NOT: %r
 ; CHECK: vfchedbs %v24, %v24, %v26
-; CHECK-NEXT: {{jno|jle}} {{\.L*}}
+; CHECK-NEXT: {{bnor|bler}} %r14
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   %call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a,
                 <2 x double> %b)
   %res = extractvalue {<2 x i64>, i32} %call, 0
   %cc = extractvalue {<2 x i64>, i32} %call, 1
   %cmp = icmp uge i32 %cc, 3
   br i1 %cmp, label %store, label %exit