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Differential D17046

AMDGPU: Document address space mapping
ClosedPublic

Authored by rivanvx on Feb 9 2016, 3:12 PM.

Details

Reviewers
• tstellarAMD
arsenm
Commits
rG3ec09e61d1c8: AMDGPU: Document address space mapping
rL265500: AMDGPU: Document address space mapping
Summary

Address space mapping is described in lib/Target/AMDGPU/AMDGPU.h in
Doxygen comments. This patch adds the description to user guide for
AMDGPU back-end.

Diff Detail

Repository
rL LLVM

Event Timeline

rivanvx updated this revision to Diff 47376.Feb 9 2016, 3:12 PM
rivanvx retitled this revision from to AMDGPU: Document address space mapping.
rivanvx updated this object.
rivanvx added reviewers: • tstellarAMD, arsenm.
arsenm added a subscriber: llvm-commits.Feb 9 2016, 3:13 PM
arsenm added inline comments.
docs/AMDGPUUsage.rst
24 ↗(On Diff #47376)

RAT0, VTX0 is only R600. I would probably just omit these

27 ↗(On Diff #47376)

The OpenCL terminology is generic. Maybe Flat (generic)?

29–30 ↗(On Diff #47376)

I would drop these two. We may change these to match HSAIL and they aren't really used.

rivanvx updated this revision to Diff 47437.Feb 10 2016, 3:59 AM

Updated per Matt's suggestions.

rivanvx marked 3 inline comments as done.Feb 10 2016, 10:32 AM

Cool, I can mark comments as done.

arsenm added inline comments.Feb 10 2016, 10:32 PM
docs/AMDGPUUsage.rst
27 ↗(On Diff #47437)

s/called flat in AMDGPU/Flat/

32–33 ↗(On Diff #47437)

There's no reason to talk about CPUs here

rivanvx updated this revision to Diff 47620.Feb 11 2016, 3:12 AM

Updated per arsenm's comments.

rivanvx marked 2 inline comments as done.Feb 11 2016, 3:13 AM

Mark as done.

rivanvx added a comment.Feb 25 2016, 1:51 PM

@arsenm is this mergeable? Any other changes I should make?

arsenm accepted this revision.Mar 1 2016, 6:32 PM
arsenm edited edge metadata.

LGTM

This revision is now accepted and ready to land.Mar 1 2016, 6:32 PM
rivanvx requested a review of this revision.Apr 4 2016, 8:08 AM
rivanvx edited edge metadata.
Closed by commit rL265500: AMDGPU: Document address space mapping (authored by tstellar). · Explain WhyApr 5 2016, 6:34 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
docs/
23 lines

Diff 52758

llvm/trunk/docs/AMDGPUUsage.rst

============================== ==============================
User Guide for AMDGPU Back-end User Guide for AMDGPU Back-end
============================== ==============================
Introduction Introduction
============ ============
The AMDGPU back-end provides ISA code generation for AMD GPUs, starting with The AMDGPU back-end provides ISA code generation for AMD GPUs, starting with
the R600 family up until the current Volcanic Islands (GCN Gen 3). the R600 family up until the current Volcanic Islands (GCN Gen 3).
Conventions
===========
Address Spaces
--------------
The AMDGPU back-end uses the following address space mapping:
============= ============================================
Address Space Memory Space
============= ============================================
0 Private
1 Global
2 Constant
3 Local
4 Generic (Flat)
5 Region
============= ============================================
The terminology in the table, aside from the region memory space, is from the
OpenCL standard.
Assembler Assembler
========= =========
The assembler is currently considered experimental. The assembler is currently considered experimental.
For syntax examples look in test/MC/AMDGPU. For syntax examples look in test/MC/AMDGPU.
Below some of the currently supported features (modulo bugs). These Below some of the currently supported features (modulo bugs). These
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