[CLANG] [AVX512] [BUILTIN] Adding prol{d|q|w}{128|256|512} builtin to clang .

[m_zuckerman]

ping

[delena]

lib/Headers/avx512vlintrin.h

35 ↗

(On Diff #47192)

The comment should be moved down - int compare is the next one.

4608 ↗

(On Diff #47192)

I thought we are adding compiler intrinsics as static inline functions.

[AsafBadouh]

lib/Headers/avx512vlintrin.h

4608 ↗

(On Diff #47192)

the second operand is "const int" that's why we used define instead of static inline function.

[delena]

LGTM

cfe/trunk/include/clang/Basic/BuiltinsX86.def

 TARGET_BUILTIN(__builtin_ia32_pmovzxbq128_mask, "V2LLiV16cV2LLiUc","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_pmovzxbq256_mask, "V4LLiV16cV4LLiUc","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_pmovzxdq128_mask, "V2LLiV4iV2LLiUc","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_pmovzxdq256_mask, "V4LLiV4iV4LLiUc","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_pmovzxwd128_mask, "V4iV8sV4iUc","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_pmovzxwd256_mask, "V8iV8sV8iUc","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_pmovzxwq128_mask, "V2LLiV8sV2LLiUc","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_pmovzxwq256_mask, "V4LLiV8sV4LLiUc","","avx512vl")
+TARGET_BUILTIN(__builtin_ia32_prold512_mask, "V16iV16iIiV16iUs","","avx512f")
+TARGET_BUILTIN(__builtin_ia32_prolq512_mask, "V8LLiV8LLiIiV8LLiUc","","avx512f")
+TARGET_BUILTIN(__builtin_ia32_prold128_mask, "V4iV4iIiV4iUc","","avx512vl")
+TARGET_BUILTIN(__builtin_ia32_prold256_mask, "V8iV8iIiV8iUc","","avx512vl")
+TARGET_BUILTIN(__builtin_ia32_prolq128_mask, "V2LLiV2LLiIiV2LLiUc","","avx512vl")
+TARGET_BUILTIN(__builtin_ia32_prolq256_mask, "V4LLiV4LLiIiV4LLiUc","","avx512vl")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN

cfe/trunk/lib/Headers/avx512fintrin.h

(__mmask8)__builtin_ia32_cmpq512_mask((__v8di)(__m512i)(a), \
                                         (__v8di)(__m512i)(b), (p), \
                                         (__mmask8)(m)); })
 
 #define _mm512_mask_cmp_epu64_mask(m, a, b, p) __extension__ ({ \
   (__mmask8)__builtin_ia32_ucmpq512_mask((__v8di)(__m512i)(a), \
                                          (__v8di)(__m512i)(b), (p), \
                                          (__mmask8)(m)); })
 
+#define _mm512_rol_epi32(a, b) __extension__ ({ \
+  (__m512i) __builtin_ia32_prold512_mask ((__v16si) (a), (b),\
+                                          (__v16si)\
+                                          _mm512_setzero_si512 (),\
+                                          (__mmask16) -1); })
+
+#define _mm512_mask_rol_epi32(W, U, a, b) __extension__ ({ \
+  (__m512i) __builtin_ia32_prold512_mask ((__v16si) (a), (b),\
+                                          (__v16si) (W),\
+                                          (__mmask16) (U)); })
+
+#define _mm512_maskz_rol_epi32(U, a, b) __extension__ ({ \
+  (__m512i) __builtin_ia32_prold512_mask ((__v16si) (a), (b),\
+                                          (__v16si)\
+                                          _mm512_setzero_si512 (),\
+                                          (__mmask16) (U)); })
+
+#define _mm512_rol_epi64(a, b) __extension__ ({ \
+  (__m512i) __builtin_ia32_prolq512_mask ((__v8di) (a), (b),\
+                                          (__v8di)\
+                                          _mm512_setzero_si512 (),\
+                                          (__mmask8) -1); })
+
+#define _mm512_mask_rol_epi64(W, U, a, b) __extension__ ({ \
+  (__m512i) __builtin_ia32_prolq512_mask ((__v8di) (a), (b),\
+                                          (__v8di) (W),\
+                                          (__mmask8) (U)); })
+
+#define _mm512_maskz_rol_epi64(U, a, b) __extension__ ({ \
+  (__m512i) __builtin_ia32_prolq512_mask ((__v8di) (a), (b),\
+                                          (__v8di)\
+                                          _mm512_setzero_si512 (),\
+                                          (__mmask8) (U)); })
+
+
 #undef __DEFAULT_FN_ATTRS
 
 #endif // __AVX512FINTRIN_H

cfe/trunk/lib/Headers/avx512vlintrin.h

 #endif
 
 #ifndef __AVX512VLINTRIN_H
 #define __AVX512VLINTRIN_H
 
 #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vl")))
 #define __DEFAULT_FN_ATTRS_BOTH __attribute__((__always_inline__, __nodebug__, __target__("avx512vl, avx512bw")))
 
+static  __inline __v2di __DEFAULT_FN_ATTRS
+_mm_setzero_di(void) {
+  return (__v2di){ 0, 0};
+}
+
 /* Integer compare */
 
 static __inline__ __mmask8 __DEFAULT_FN_ATTRS_BOTH
 _mm_cmpeq_epi32_mask(__m128i __a, __m128i __b) {
   return (__mmask8)__builtin_ia32_pcmpeqd128_mask((__v4si)__a, (__v4si)__b,
                                                   (__mmask8)-1);
 }
 

 {
   return (__m256i) __builtin_ia32_pmovzxwq256_mask ((__v8hi) __A,
                 (__v4di)
                 _mm256_setzero_si256 (),
                 (__mmask8) __U);
 }
 
 
+#define _mm_rol_epi32(a, b) __extension__ ({\
+   (__m128i)__builtin_ia32_prold128_mask((__v4si) (a), (b),\
+                                         (__v4si)\
+                                         _mm_setzero_si128 (),\
+                                         (__mmask8) -1); })
+
+#define _mm_mask_rol_epi32(w, u, a, b) __extension__ ({\
+   (__m128i)__builtin_ia32_prold128_mask((__v4si) (a), (b),\
+                                         (__v4si) (w),\
+                                         (__mmask8) (u)); })
+
+#define _mm_maskz_rol_epi32(u, a, b) __extension__ ({\
+   (__m128i)__builtin_ia32_prold128_mask((__v4si) (a), (b),\
+                                         (__v4si)\
+                                         _mm_setzero_si128 (),\
+                                         (__mmask8) (u)); })
+
+#define _mm256_rol_epi32(a, b) __extension__ ({\
+   (__m256i)__builtin_ia32_prold256_mask((__v8si) (a), (b),\
+                                         (__v8si)\
+                                         _mm256_setzero_si256 (),\
+                                         (__mmask8) -1); })
+
+#define _mm256_mask_rol_epi32(w, u, a, b) __extension__ ({\
+   (__m256i)__builtin_ia32_prold256_mask((__v8si) (a), (b),\
+                                         (__v8si) (w),\
+                                         (__mmask8) (u)); })
+
+#define _mm256_maskz_rol_epi32(u, a, b) __extension__ ({\
+   (__m256i)__builtin_ia32_prold256_mask((__v8si) (a), (b),\
+                                         (__v8si)\
+                                         _mm256_setzero_si256 (),\
+                                         (__mmask8) (u)); })
+
+#define _mm_rol_epi64(a, b) _extension__ ({\
+   (__m128i)__builtin_ia32_prolq128_mask((__v2di) (a), (b),\
+                                         (__v2di)\
+                                         _mm_setzero_di (),\
+                                         (__mmask8) -1); })
+
+#define _mm_mask_rol_epi64(w, u, a, b) __extension__ ({\
+   (__m128i)__builtin_ia32_prolq128_mask((__v2di) (a), (b),\
+                                         (__v2di) (w),\
+                                         (__mmask8) (u)); })
+
+#define _mm_maskz_rol_epi64(u, a, b) __extension__ ({\
+   (__m128i)__builtin_ia32_prolq128_mask((__v2di) (a), (b),\
+                                         (__v2di)\
+                                         _mm_setzero_di(),\
+                                         (__mmask8) (u)); })
+
+#define _mm256_rol_epi64(a, b) __extension__ ({\
+   (__m256i)__builtin_ia32_prolq256_mask((__v4di) (a), (b),\
+                                         (__v4di)\
+                                         _mm256_setzero_si256 (),\
+                                         (__mmask8) -1); })
+
+#define _mm256_mask_rol_epi64(w, u, a, b) __extension__ ({\
+   (__m256i)__builtin_ia32_prolq256_mask((__v4di) (a), (b),\
+                                         (__v4di) (w),\
+                                         (__mmask8) (u)); })
+
+#define _mm256_maskz_rol_epi64(u, a, b) __extension__ ({\
+   (__m256i)__builtin_ia32_prolq256_mask((__v4di) (a), (b),\
+                                         (__v4di)\
+                                         _mm256_setzero_si256 (),\
+                                         (__mmask8) (u)); })
+
 #undef __DEFAULT_FN_ATTRS
 #undef __DEFAULT_FN_ATTRS_BOTH
 
 #endif /* __AVX512VLINTRIN_H */

cfe/trunk/test/CodeGen/avx512f-builtins.c

__m512i test_mm512_mask_cvtepu16_epi64(__m512i __W, __mmask8 __U, __m128i __A) {
   // CHECK: @llvm.x86.avx512.mask.pmovzxw.q.512
   return _mm512_mask_cvtepu16_epi64(__W, __U, __A); 
 }
 
 __m512i test_mm512_maskz_cvtepu16_epi64(__mmask8 __U, __m128i __A) {
   // CHECK-LABEL: @test_mm512_maskz_cvtepu16_epi64
   // CHECK: @llvm.x86.avx512.mask.pmovzxw.q.512
   return _mm512_maskz_cvtepu16_epi64(__U, __A); 
-}
+}
+
+
+__m512i test_mm512_rol_epi32(__m512i __A) {
+  // CHECK-LABEL: @test_mm512_rol_epi32
+  // CHECK: @llvm.x86.avx512.mask.prol.d.512
+  return _mm512_rol_epi32(__A, 5); 
+}
+
+__m512i test_mm512_mask_rol_epi32(__m512i __W, __mmask16 __U, __m512i __A) {
+  // CHECK-LABEL: @test_mm512_mask_rol_epi32
+  // CHECK: @llvm.x86.avx512.mask.prol.d.512
+  return _mm512_mask_rol_epi32(__W, __U, __A, 5); 
+}
+
+__m512i test_mm512_maskz_rol_epi32(__mmask16 __U, __m512i __A) {
+  // CHECK-LABEL: @test_mm512_maskz_rol_epi32
+  // CHECK: @llvm.x86.avx512.mask.prol.d.512
+  return _mm512_maskz_rol_epi32(__U, __A, 5); 
+}
+
+__m512i test_mm512_rol_epi64(__m512i __A) {
+  // CHECK-LABEL: @test_mm512_rol_epi64
+  // CHECK: @llvm.x86.avx512.mask.prol.q.512
+  return _mm512_rol_epi64(__A, 5); 
+}
+
+__m512i test_mm512_mask_rol_epi64(__m512i __W, __mmask8 __U, __m512i __A) {
+  // CHECK-LABEL: @test_mm512_mask_rol_epi64
+  // CHECK: @llvm.x86.avx512.mask.prol.q.512
+  return _mm512_mask_rol_epi64(__W, __U, __A, 5); 
+}
+
+__m512i test_mm512_maskz_rol_epi64(__mmask8 __U, __m512i __A) {
+  // CHECK-LABEL: @test_mm512_maskz_rol_epi64
+  // CHECK: @llvm.x86.avx512.mask.prol.q.512
+  return _mm512_maskz_rol_epi64(__U, __A, 5); 
+}

cfe/trunk/test/CodeGen/avx512vl-builtins.c

__m256i test_mm256_mask_cvtepu16_epi64(__m256i __W, __mmask8 __U, __m128i __A) {
   // CHECK: @llvm.x86.avx512.mask.pmovzxw.q.256
   return _mm256_mask_cvtepu16_epi64(__W, __U, __A); 
 }
 
 __m256i test_mm256_maskz_cvtepu16_epi64(__mmask8 __U, __m128i __A) {
   // CHECK-LABEL: @test_mm256_maskz_cvtepu16_epi64
   // CHECK: @llvm.x86.avx512.mask.pmovzxw.q.256
   return _mm256_maskz_cvtepu16_epi64(__U, __A); 
-}
+}
+
+__m128i test_mm_rol_epi32(__m128i __A) {
+  // CHECK-LABEL: @test_mm_rol_epi32
+  // CHECK: @llvm.x86.avx512.mask.prol.d.128
+  return _mm_rol_epi32(__A, 5); 
+}
+
+__m128i test_mm_mask_rol_epi32(__m128i __W, __mmask8 __U, __m128i __A) {
+  // CHECK-LABEL: @test_mm_mask_rol_epi32
+  // CHECK: @llvm.x86.avx512.mask.prol.d.128
+  return _mm_mask_rol_epi32(__W, __U, __A, 5); 
+}
+
+__m128i test_mm_maskz_rol_epi32(__mmask8 __U, __m128i __A) {
+  // CHECK-LABEL: @test_mm_maskz_rol_epi32
+  // CHECK: @llvm.x86.avx512.mask.prol.d.128
+  return _mm_maskz_rol_epi32(__U, __A, 5); 
+}
+
+__m256i test_mm256_rol_epi32(__m256i __A) {
+  // CHECK-LABEL: @test_mm256_rol_epi32
+  // CHECK: @llvm.x86.avx512.mask.prol.d.256
+  return _mm256_rol_epi32(__A, 5); 
+}
+
+__m256i test_mm256_mask_rol_epi32(__m256i __W, __mmask8 __U, __m256i __A) {
+  // CHECK-LABEL: @test_mm256_mask_rol_epi32
+  // CHECK: @llvm.x86.avx512.mask.prol.d.256
+  return _mm256_mask_rol_epi32(__W, __U, __A, 5); 
+}
+
+__m256i test_mm256_maskz_rol_epi32(__mmask8 __U, __m256i __A) {
+  // CHECK-LABEL: @test_mm256_maskz_rol_epi32
+  // CHECK: @llvm.x86.avx512.mask.prol.d.256
+  return _mm256_maskz_rol_epi32(__U, __A, 5); 
+}
+
+__m128i test_mm_rol_epi64(__m128i __A) {
+  // CHECK-LABEL: @test_mm_rol_epi64
+  // CHECK: @llvm.x86.avx512.mask.prol.q.128
+  return _mm_rol_epi64(__A, 5); 
+}
+
+__m128i test_mm_mask_rol_epi64(__m128i __W, __mmask8 __U, __m128i __A) {
+  // CHECK-LABEL: @test_mm_mask_rol_epi64
+  // CHECK: @llvm.x86.avx512.mask.prol.q.128
+  return _mm_mask_rol_epi64(__W, __U, __A, 5); 
+}
+
+__m128i test_mm_maskz_rol_epi64(__mmask8 __U, __m128i __A) {
+  // CHECK-LABEL: @test_mm_maskz_rol_epi64
+  // CHECK: @llvm.x86.avx512.mask.prol.q.128
+  return _mm_maskz_rol_epi64(__U, __A, 5); 
+}
+
+__m256i test_mm256_rol_epi64(__m256i __A) {
+  // CHECK-LABEL: @test_mm256_rol_epi64
+  // CHECK: @llvm.x86.avx512.mask.prol.q.256
+  return _mm256_rol_epi64(__A, 5); 
+}
+
+__m256i test_mm256_mask_rol_epi64(__m256i __W, __mmask8 __U, __m256i __A) {
+  // CHECK-LABEL: @test_mm256_mask_rol_epi64
+  // CHECK: @llvm.x86.avx512.mask.prol.q.256
+  return _mm256_mask_rol_epi64(__W, __U, __A, 5); 
+}
+
+__m256i test_mm256_maskz_rol_epi64(__mmask8 __U, __m256i __A) {
+  // CHECK-LABEL: @test_mm256_maskz_rol_epi64
+  // CHECK: @llvm.x86.avx512.mask.prol.q.256
+  return _mm256_maskz_rol_epi64(__U, __A, 5); 
+}