Require MachineFunctionPasses to declare their support for virtual registers.

[dschuff]

Summary

Not ready for commit yet; only includes X86 and WebAssembly.
Adds a method to MachineFunctionPass for derived classes to declare that they
support virtual registers, and an assert in the base runOnFunction to
enforce it. The idea is to make it more clear which passes support virtual
registers and to avoid accidentally exposing VRegs to passes which aren't
prepared to handle them.

[dschuff]

Ping. any comments on the general approach or specific mechanism used here?

[dschuff]

+@hfinkel because of his comment on D16481 and the mailing list

[hfinkel]

include/llvm/CodeGen/MachineFunctionPass.h

61

I think that what you gain in brevity you lose in clarity, because while the macro is shorter than the function call, it is now not immediately obvious what it does. Just include the function override.

An alternative is to make it an argument to the MachineFunctionPass constructor.

Also, I'm not entirely sure this is a problem worth solving, at least not as a one-off. We already have passes that only work either before or after register allocation, in or not in SSA form, before or after PHI elimination, etc. -- and we don't explicitly declare any of that.

Generically, it would be nice to express these dependencies in a more-consistent way, and I'm in favor of something that let's us do that. We already have a facility in the pass manager to express requirements, maybe we can build on that?

[dschuff]

include/llvm/CodeGen/MachineFunctionPass.h

61

Yeah it was my intention to expand the macros manually (and fill in the rest of the architectures) before committing. I guess I mentioned that in the mailing list post but not here.

As for general requirements, that's not a bad idea either. I toyed with making this a sort of pseudo analysis, but if we made some other notion about properties of the MIR at a particular time (is SSA, has virtual registers, etc) that would fit.

[qcolombet]

Hi Derek,

I’m catching up with emails now.
I think I’ll get to this (and your other thread) next week.

Cheers,
-Quentin

[qcolombet]

include/llvm/CodeGen/MachineFunctionPass.h

61

I toyed with making this a sort of pseudo analysis, but if we made some other notion about properties of the MIR at a particular time (is SSA, has virtual registers, etc) that would fit.

I didn’t get that. I am guessing you wanted to say “wouldn’t fit” since the pass manager has currently no way to tell what happened at a particular time.

Anyhow, for the problem we are trying to solve, I am not sure a single boolean is enough. For instance, the peephole optimizer supports virtual registers, but only works on SSA code. I agree with Hal that what we want is a way to express dependencies in a more-consistent way.

To get concrete here, I think that we could start with some properties on the MachineFunction (like isSSA). Then, the machine verifier would check the assumptions are correct based on them, like after register allocation we don’t have any virtual registers anymore. Other passes would have a way to express what they support based on those properties. Finally, if we try to schedule a pass whereas the properties do not match what it supports, this is an error.

[dschuff]

I investigated a more generic mechanism and its requirements in D18421, have a look.

[dschuff]

Superseded by D18421

include/llvm/CodeGen/EdgeBundles.h

class EdgeBundles : public MachineFunctionPass {
   IntEqClasses EC;
 
   /// Blocks - Map each bundle to a list of basic block numbers.
   SmallVector<SmallVector<unsigned, 8>, 4> Blocks;
 
 public:
   static char ID;
   EdgeBundles() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 
   /// getBundle - Return the ingoing (Out = false) or outgoing (Out = true)
   /// bundle number for basic block #N
   unsigned getBundle(unsigned N, bool Out) const { return EC[2 * N + Out]; }
 
   /// getNumBundles - Return the total number of bundles in the CFG.
   unsigned getNumBundles() const { return EC.getNumClasses(); }
 

include/llvm/CodeGen/LiveIntervalAnalysis.h

class LiveIntervals : public MachineFunctionPass {
 
     /// Keeps a live range set for each register unit to track fixed physreg
     /// interference.
     SmallVector<LiveRange*, 0> RegUnitRanges;
 
   public:
     static char ID; // Pass identification, replacement for typeid
     LiveIntervals();
+    SUPPORTS_VIRTUAL_REGISTERS
     ~LiveIntervals() override;
 
     // Calculate the spill weight to assign to a single instruction.
     static float getSpillWeight(bool isDef, bool isUse,
                                 const MachineBlockFrequencyInfo *MBFI,
                                 const MachineInstr *Instr);
 
     LiveInterval &getInterval(unsigned Reg) {

include/llvm/CodeGen/LiveRegMatrix.h

class LiveRegMatrix : public MachineFunctionPass {
 
   // MachineFunctionPass boilerplate.
   void getAnalysisUsage(AnalysisUsage&) const override;
   bool runOnMachineFunction(MachineFunction&) override;
   void releaseMemory() override;
 public:
   static char ID;
   LiveRegMatrix();
+  SUPPORTS_VIRTUAL_REGISTERS
 
   //===--------------------------------------------------------------------===//
   // High-level interface.
   //===--------------------------------------------------------------------===//
   //
   // Check for interference before assigning virtual registers to physical
   // registers.
   //

include/llvm/CodeGen/LiveStackAnalysis.h

class LiveStacks : public MachineFunctionPass {
   /// S2RCMap - Stack slot indices to register class mapping.
   std::map<int, const TargetRegisterClass *> S2RCMap;
 
 public:
   static char ID; // Pass identification, replacement for typeid
   LiveStacks() : MachineFunctionPass(ID) {
     initializeLiveStacksPass(*PassRegistry::getPassRegistry());
   }
+  SUPPORTS_VIRTUAL_REGISTERS
 
   typedef SS2IntervalMap::iterator iterator;
   typedef SS2IntervalMap::const_iterator const_iterator;
   const_iterator begin() const { return S2IMap.begin(); }
   const_iterator end() const { return S2IMap.end(); }
   iterator begin() { return S2IMap.begin(); }
   iterator end() { return S2IMap.end(); }
 

include/llvm/CodeGen/LiveVariables.h

 class MachineRegisterInfo;
 
 class LiveVariables : public MachineFunctionPass {
 public:
   static char ID; // Pass identification, replacement for typeid
   LiveVariables() : MachineFunctionPass(ID) {
     initializeLiveVariablesPass(*PassRegistry::getPassRegistry());
   }
+  SUPPORTS_VIRTUAL_REGISTERS
 
   /// VarInfo - This represents the regions where a virtual register is live in
   /// the program.  We represent this with three different pieces of
   /// information: the set of blocks in which the instruction is live
   /// throughout, the set of blocks in which the instruction is actually used,
   /// and the set of non-phi instructions that are the last users of the value.
   ///
   /// In the common case where a value is defined and killed in the same block,

include/llvm/CodeGen/MachineBlockFrequencyInfo.h

 class MachineBlockFrequencyInfo : public MachineFunctionPass {
   typedef BlockFrequencyInfoImpl<MachineBasicBlock> ImplType;
   std::unique_ptr<ImplType> MBFI;
 
 public:
   static char ID;
 
   MachineBlockFrequencyInfo();
+  SUPPORTS_VIRTUAL_REGISTERS
 
   ~MachineBlockFrequencyInfo() override;
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
   void releaseMemory() override;

include/llvm/CodeGen/MachineDominanceFrontier.h

public:
   typedef DominanceFrontierBase<MachineBasicBlock>::const_iterator const_iterator;
 
   void operator=(const MachineDominanceFrontier &) = delete;
   MachineDominanceFrontier(const MachineDominanceFrontier &) = delete;
 
   static char ID;
 
   MachineDominanceFrontier();
+  SUPPORTS_VIRTUAL_REGISTERS
 
   DominanceFrontierBase<MachineBasicBlock> &getBase() {
     return Base;
   }
 
   inline const std::vector<MachineBasicBlock*> &getRoots() const {
     return Base.getRoots();
   }

include/llvm/CodeGen/MachineDominators.h

class MachineDominatorTree : public MachineFunctionPass {
   /// This updates the underlying DT information in a way that uses
   /// the fast query path of DT as much as possible.
   ///
   /// \post CriticalEdgesToSplit.empty().
   void applySplitCriticalEdges() const;
 
 public:
   static char ID; // Pass ID, replacement for typeid
+  SUPPORTS_VIRTUAL_REGISTERS
   DominatorTreeBase<MachineBasicBlock>* DT;
 
   MachineDominatorTree();
 
   ~MachineDominatorTree() override;
 
   DominatorTreeBase<MachineBasicBlock> &getBase() {
     applySplitCriticalEdges();

include/llvm/CodeGen/MachineFunctionPass.h

protected:
   /// getAnalysisUsage - Subclasses that override getAnalysisUsage
   /// must call this.
   ///
   /// For MachineFunctionPasses, calling AU.preservesCFG() indicates that
   /// the pass does not modify the MachineBasicBlock CFG.
   ///
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
+  const bool SupportsVirtualRegisters = false;
+  virtual bool getSupportsVirtualRegisters() const { return false;}
+
 private:
   /// createPrinterPass - Get a machine function printer pass.
   Pass *createPrinterPass(raw_ostream &O,
                           const std::string &Banner) const override;
 
   bool runOnFunction(Function &F) override;
 };
 
 } // End llvm namespace
+#define SUPPORTS_VIRTUAL_REGISTERS   bool getSupportsVirtualRegisters() const override { return true; }
 
 #endif

include/llvm/CodeGen/MachineLoopInfo.h

class MachineLoopInfo : public MachineFunctionPass {
   MachineLoopInfo(const MachineLoopInfo &) = delete;
 
 public:
   static char ID; // Pass identification, replacement for typeid
 
   MachineLoopInfo() : MachineFunctionPass(ID) {
     initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
   }
+  SUPPORTS_VIRTUAL_REGISTERS
 
   LoopInfoBase<MachineBasicBlock, MachineLoop>& getBase() { return LI; }
 
   /// iterator/begin/end - The interface to the top-level loops in the current
   /// function.
   ///
   typedef LoopInfoBase<MachineBasicBlock, MachineLoop>::iterator iterator;
   inline iterator begin() const { return LI.begin(); }

include/llvm/CodeGen/MachinePostDominators.h

 struct MachinePostDominatorTree : public MachineFunctionPass {
 private:
   DominatorTreeBase<MachineBasicBlock> *DT;
 
 public:
   static char ID;
 
   MachinePostDominatorTree();
+  SUPPORTS_VIRTUAL_REGISTERS
 
   ~MachinePostDominatorTree() override;
 
   FunctionPass *createMachinePostDominatorTreePass();
 
   const std::vector<MachineBasicBlock *> &getRoots() const {
     return DT->getRoots();
   }

include/llvm/CodeGen/MachineTraceMetrics.h

class MachineTraceMetrics : public MachineFunctionPass {
   const MachineLoopInfo *Loops;
   TargetSchedModel SchedModel;
 
 public:
   class Ensemble;
   class Trace;
   static char ID;
   MachineTraceMetrics();
+  SUPPORTS_VIRTUAL_REGISTERS
   void getAnalysisUsage(AnalysisUsage&) const override;
   bool runOnMachineFunction(MachineFunction&) override;
   void releaseMemory() override;
   void verifyAnalysis() const override;
 
   friend class Ensemble;
   friend class Trace;
 

include/llvm/CodeGen/SlotIndexes.h

IndexListEntry* createEntry(MachineInstr *mi, unsigned index) {
       return entry;
     }
 
     /// Renumber locally after inserting curItr.
     void renumberIndexes(IndexList::iterator curItr);
 
   public:
     static char ID;
+    SUPPORTS_VIRTUAL_REGISTERS
 
     SlotIndexes() : MachineFunctionPass(ID) {
       initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
     }
 
     ~SlotIndexes() {
       // The indexList's nodes are all allocated in the BumpPtrAllocator.
       indexList.clearAndLeakNodesUnsafely();

include/llvm/CodeGen/VirtRegMap.h

private:
 
     VirtRegMap(const VirtRegMap&) = delete;
     void operator=(const VirtRegMap&) = delete;
 
   public:
     static char ID;
     VirtRegMap() : MachineFunctionPass(ID), Virt2PhysMap(NO_PHYS_REG),
                    Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) { }
+    SUPPORTS_VIRTUAL_REGISTERS
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesAll();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
     MachineFunction &getMachineFunction() const {

lib/CodeGen/BranchFolding.cpp

TailMergeSize("tail-merge-size",
                               cl::init(3), cl::Hidden);
 
 namespace {
   /// BranchFolderPass - Wrap branch folder in a machine function pass.
   class BranchFolderPass : public MachineFunctionPass {
   public:
     static char ID;
     explicit BranchFolderPass(): MachineFunctionPass(ID) {}
+    SUPPORTS_VIRTUAL_REGISTERS
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.addRequired<MachineBlockFrequencyInfo>();
       AU.addRequired<MachineBranchProbabilityInfo>();
       AU.addRequired<TargetPassConfig>();
       MachineFunctionPass::getAnalysisUsage(AU);

lib/CodeGen/DeadMachineInstructionElim.cpp

class DeadMachineInstructionElim : public MachineFunctionPass {
     const TargetInstrInfo *TII;
     BitVector LivePhysRegs;
 
   public:
     static char ID; // Pass identification, replacement for typeid
     DeadMachineInstructionElim() : MachineFunctionPass(ID) {
      initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry());
     }
+    SUPPORTS_VIRTUAL_REGISTERS
 
   private:
     bool isDead(const MachineInstr *MI) const;
   };
 }
 char DeadMachineInstructionElim::ID = 0;
 char &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID;
 

lib/CodeGen/EarlyIfConversion.cpp

class EarlyIfConverter : public MachineFunctionPass {
   MachineLoopInfo *Loops;
   MachineTraceMetrics *Traces;
   MachineTraceMetrics::Ensemble *MinInstr;
   SSAIfConv IfConv;
 
 public:
   static char ID;
   EarlyIfConverter() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
   void getAnalysisUsage(AnalysisUsage &AU) const override;
   bool runOnMachineFunction(MachineFunction &MF) override;
   const char *getPassName() const override { return "Early If-Conversion"; }
 
 private:
   bool tryConvertIf(MachineBasicBlock*);
   void updateDomTree(ArrayRef<MachineBasicBlock*> Removed);
   void updateLoops(ArrayRef<MachineBasicBlock*> Removed);

lib/CodeGen/ExpandISelPseudos.cpp

public:
     ExpandISelPseudos() : MachineFunctionPass(ID) {}
 
   private:
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
+    SUPPORTS_VIRTUAL_REGISTERS
   };
 } // end anonymous namespace
 
 char ExpandISelPseudos::ID = 0;
 char &llvm::ExpandISelPseudosID = ExpandISelPseudos::ID;
 INITIALIZE_PASS(ExpandISelPseudos, "expand-isel-pseudos",
                 "Expand ISel Pseudo-instructions", false, false)
 

lib/CodeGen/ExpandPostRAPseudos.cpp

 struct ExpandPostRA : public MachineFunctionPass {
 private:
   const TargetRegisterInfo *TRI;
   const TargetInstrInfo *TII;
 
 public:
   static char ID; // Pass identification, replacement for typeid
   ExpandPostRA() : MachineFunctionPass(ID) {}
+  // LowerSubregToReg expects physical registers and has assertions to validate
+  // the expectation. LowerCopy delegates to the target and supports virtual
+  // registers if the target does.
+  SUPPORTS_VIRTUAL_REGISTERS
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addPreservedID(MachineLoopInfoID);
     AU.addPreservedID(MachineDominatorsID);
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 

lib/CodeGen/LiveDebugVariables.h

class LLVM_LIBRARY_VISIBILITY LiveDebugVariables : public MachineFunctionPass {
   void *pImpl;
 
 public:
   static char ID; // Pass identification, replacement for typeid
 
   LiveDebugVariables();
   ~LiveDebugVariables() override;
 
+  SUPPORTS_VIRTUAL_REGISTERS
+
   /// renameRegister - Move any user variables in OldReg to NewReg:SubIdx.
   /// @param OldReg Old virtual register that is going away.
   /// @param NewReg New register holding the user variables.
   /// @param SubIdx If NewReg is a virtual register, SubIdx may indicate a sub-
   ///               register.
   void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
 
   /// splitRegister - Move any user variables in OldReg to the live ranges in

lib/CodeGen/LocalStackSlotAllocation.cpp

void AssignProtectedObjSet(const StackObjSet &UnassignedObjs,
                                int64_t &Offset, unsigned &MaxAlign);
     void calculateFrameObjectOffsets(MachineFunction &Fn);
     bool insertFrameReferenceRegisters(MachineFunction &Fn);
   public:
     static char ID; // Pass identification, replacement for typeid
     explicit LocalStackSlotPass() : MachineFunctionPass(ID) { 
       initializeLocalStackSlotPassPass(*PassRegistry::getPassRegistry());
     }
+    SUPPORTS_VIRTUAL_REGISTERS
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       AU.addRequired<StackProtector>();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 

lib/CodeGen/MIRPrintingPass.cpp

 /// serialization format.
 struct MIRPrintingPass : public MachineFunctionPass {
   static char ID;
   raw_ostream &OS;
   std::string MachineFunctions;
 
   MIRPrintingPass() : MachineFunctionPass(ID), OS(dbgs()) {}
   MIRPrintingPass(raw_ostream &OS) : MachineFunctionPass(ID), OS(OS) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 
   const char *getPassName() const override { return "MIR Printing Pass"; }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesAll();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 

lib/CodeGen/MachineBlockPlacement.cpp

void rotateLoopWithProfile(BlockChain &LoopChain, MachineLoop &L,
                              const BlockFilterSet &LoopBlockSet);
   void buildCFGChains(MachineFunction &F);
 
 public:
   static char ID; // Pass identification, replacement for typeid
   MachineBlockPlacement() : MachineFunctionPass(ID) {
     initializeMachineBlockPlacementPass(*PassRegistry::getPassRegistry());
   }
+  SUPPORTS_VIRTUAL_REGISTERS
 
   bool runOnMachineFunction(MachineFunction &F) override;
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<MachineBranchProbabilityInfo>();
     AU.addRequired<MachineBlockFrequencyInfo>();
     AU.addRequired<MachineDominatorTree>();
     AU.addRequired<MachineLoopInfo>();

lib/CodeGen/MachineCSE.cpp

class MachineCSE : public MachineFunctionPass {
     AliasAnalysis *AA;
     MachineDominatorTree *DT;
     MachineRegisterInfo *MRI;
   public:
     static char ID; // Pass identification
     MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(0), CurrVN(0) {
       initializeMachineCSEPass(*PassRegistry::getPassRegistry());
     }
+    SUPPORTS_VIRTUAL_REGISTERS
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
       AU.addRequired<AAResultsWrapperPass>();
       AU.addPreservedID(MachineLoopInfoID);

lib/CodeGen/MachineCombiner.cpp

class MachineCombiner : public MachineFunctionPass {
   /// True if optimizing for code size.
   bool OptSize;
 
 public:
   static char ID;
   MachineCombiner() : MachineFunctionPass(ID) {
     initializeMachineCombinerPass(*PassRegistry::getPassRegistry());
   }
+  SUPPORTS_VIRTUAL_REGISTERS
   void getAnalysisUsage(AnalysisUsage &AU) const override;
   bool runOnMachineFunction(MachineFunction &MF) override;
   const char *getPassName() const override { return "Machine InstCombiner"; }
 
 private:
   bool doSubstitute(unsigned NewSize, unsigned OldSize);
   bool combineInstructions(MachineBasicBlock *);
   MachineInstr *getOperandDef(const MachineOperand &MO);

lib/CodeGen/MachineFunctionPass.cpp

 #include "llvm/Analysis/DominanceFrontier.h"
 #include "llvm/Analysis/GlobalsModRef.h"
 #include "llvm/Analysis/IVUsers.h"
 #include "llvm/Analysis/LoopInfo.h"
 #include "llvm/Analysis/MemoryDependenceAnalysis.h"
 #include "llvm/Analysis/ScalarEvolution.h"
 #include "llvm/Analysis/ScalarEvolutionAliasAnalysis.h"
 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/StackProtector.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/Function.h"
 using namespace llvm;
 
 Pass *MachineFunctionPass::createPrinterPass(raw_ostream &O,
                                              const std::string &Banner) const {
   return createMachineFunctionPrinterPass(O, Banner);
 }
 
 bool MachineFunctionPass::runOnFunction(Function &F) {
   // Do not codegen any 'available_externally' functions at all, they have
   // definitions outside the translation unit.
   if (F.hasAvailableExternallyLinkage())
     return false;
 
   MachineFunction &MF = getAnalysis<MachineFunctionAnalysis>().getMF();
+  assert(getSupportsVirtualRegisters() || !MF.getRegInfo().getNumVirtRegs() &&
+         "Pass does not support virtual registers");
   return runOnMachineFunction(MF);
 }
 
 void MachineFunctionPass::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addRequired<MachineFunctionAnalysis>();
   AU.addPreserved<MachineFunctionAnalysis>();
 
   // MachineFunctionPass preserves all LLVM IR passes, but there's no

lib/CodeGen/MachineFunctionPrinterPass.cpp

struct MachineFunctionPrinterPass : public MachineFunctionPass {
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     if (!llvm::isFunctionInPrintList(MF.getName()))
       return false;
     OS << "# " << Banner << ":\n";
     MF.print(OS, getAnalysisIfAvailable<SlotIndexes>());
     return false;
   }
+  SUPPORTS_VIRTUAL_REGISTERS
 };
 
 char MachineFunctionPrinterPass::ID = 0;
 }
 
 char &llvm::MachineFunctionPrinterPassID = MachineFunctionPrinterPass::ID;
 INITIALIZE_PASS(MachineFunctionPrinterPass, "machineinstr-printer",
                 "Machine Function Printer", false, false)

lib/CodeGen/MachineLICM.cpp

class MachineLICM : public MachineFunctionPass {
     unsigned SpeculationState;
 
   public:
     static char ID; // Pass identification, replacement for typeid
     MachineLICM() :
       MachineFunctionPass(ID), PreRegAlloc(true) {
         initializeMachineLICMPass(*PassRegistry::getPassRegistry());
       }
+    SUPPORTS_VIRTUAL_REGISTERS
 
     explicit MachineLICM(bool PreRA) :
       MachineFunctionPass(ID), PreRegAlloc(PreRA) {
         initializeMachineLICMPass(*PassRegistry::getPassRegistry());
       }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 

lib/CodeGen/MachineScheduler.cpp

 protected:
   void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags);
 };
 
 /// MachineScheduler runs after coalescing and before register allocation.
 class MachineScheduler : public MachineSchedulerBase {
 public:
   MachineScheduler();
+  SUPPORTS_VIRTUAL_REGISTERS
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   bool runOnMachineFunction(MachineFunction&) override;
 
   static char ID; // Class identification, replacement for typeinfo
 
 protected:

lib/CodeGen/MachineSink.cpp

class MachineSinking : public MachineFunctionPass {
     typedef std::map<MachineBasicBlock *, SmallVector<MachineBasicBlock *, 4>>
         AllSuccsCache;
 
   public:
     static char ID; // Pass identification
     MachineSinking() : MachineFunctionPass(ID) {
       initializeMachineSinkingPass(*PassRegistry::getPassRegistry());
     }
+    SUPPORTS_VIRTUAL_REGISTERS
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
       AU.addRequired<AAResultsWrapperPass>();
       AU.addRequired<MachineDominatorTree>();

lib/CodeGen/MachineVerifier.cpp

namespace {
   struct MachineVerifierPass : public MachineFunctionPass {
     static char ID; // Pass ID, replacement for typeid
     const std::string Banner;
 
     MachineVerifierPass(const std::string &banner = nullptr)
       : MachineFunctionPass(ID), Banner(banner) {
         initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
       }
+    SUPPORTS_VIRTUAL_REGISTERS
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesAll();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
     bool runOnMachineFunction(MachineFunction &MF) override {
       MF.verify(this, Banner.c_str());

lib/CodeGen/OptimizePHIs.cpp

class OptimizePHIs : public MachineFunctionPass {
     MachineRegisterInfo *MRI;
     const TargetInstrInfo *TII;
 
   public:
     static char ID; // Pass identification
     OptimizePHIs() : MachineFunctionPass(ID) {
       initializeOptimizePHIsPass(*PassRegistry::getPassRegistry());
     }
+    SUPPORTS_VIRTUAL_REGISTERS
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 

lib/CodeGen/PHIElimination.cpp

class PHIElimination : public MachineFunctionPass {
     LiveVariables *LV;
     LiveIntervals *LIS;
 
   public:
     static char ID; // Pass identification, replacement for typeid
     PHIElimination() : MachineFunctionPass(ID) {
       initializePHIEliminationPass(*PassRegistry::getPassRegistry());
     }
+    SUPPORTS_VIRTUAL_REGISTERS
 
     bool runOnMachineFunction(MachineFunction &Fn) override;
     void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   private:
     /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
     /// in predecessor basic blocks.
     ///

lib/CodeGen/PeepholeOptimizer.cpp

class PeepholeOptimizer : public MachineFunctionPass {
     MachineRegisterInfo   *MRI;
     MachineDominatorTree  *DT;  // Machine dominator tree
 
   public:
     static char ID; // Pass identification
     PeepholeOptimizer() : MachineFunctionPass(ID) {
       initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
     }
+    SUPPORTS_VIRTUAL_REGISTERS
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
       if (Aggressive) {
         AU.addRequired<MachineDominatorTree>();

lib/CodeGen/ProcessImplicitDefs.cpp

class ProcessImplicitDefs : public MachineFunctionPass {
   bool canTurnIntoImplicitDef(MachineInstr *MI);
 
 public:
   static char ID;
 
   ProcessImplicitDefs() : MachineFunctionPass(ID) {
     initializeProcessImplicitDefsPass(*PassRegistry::getPassRegistry());
   }
+  SUPPORTS_VIRTUAL_REGISTERS
 
   void getAnalysisUsage(AnalysisUsage &au) const override;
 
   bool runOnMachineFunction(MachineFunction &fn) override;
 };
 } // end anonymous namespace
 
 char ProcessImplicitDefs::ID = 0;

lib/CodeGen/PrologEpilogInserter.cpp

bool PEI::runOnMachineFunction(MachineFunction &Fn) {
   // Replace all MO_FrameIndex operands with physical register references
   // and actual offsets.
   //
   replaceFrameIndices(Fn);
 
   // If register scavenging is needed, as we've enabled doing it as a
   // post-pass, scavenge the virtual registers that frame index elimination
   // inserted.
-  if (TRI->requiresRegisterScavenging(Fn) && FrameIndexVirtualScavenging)
+  if (FrameIndexVirtualScavenging)
     scavengeFrameVirtualRegs(Fn);
 
   // Clear any vregs created by virtual scavenging.
   Fn.getRegInfo().clearVirtRegs();
 
   // Warn on stack size when we exceeds the given limit.
   MachineFrameInfo *MFI = Fn.getFrameInfo();
   uint64_t StackSize = MFI->getStackSize();

lib/CodeGen/RegAllocBasic.cpp

std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
                       CompSpillWeight> Queue;
 
   // Scratch space.  Allocated here to avoid repeated malloc calls in
   // selectOrSplit().
   BitVector UsableRegs;
 
 public:
   RABasic();
+  SUPPORTS_VIRTUAL_REGISTERS
 
   /// Return the pass name.
   const char* getPassName() const override {
     return "Basic Register Allocator";
   }
 
   /// RABasic analysis usage.
   void getAnalysisUsage(AnalysisUsage &AU) const override;

lib/CodeGen/RegAllocFast.cpp

static RegisterRegAlloc
   fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
 
 namespace {
   class RAFast : public MachineFunctionPass {
   public:
     static char ID;
     RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
                isBulkSpilling(false) {}
+    SUPPORTS_VIRTUAL_REGISTERS
   private:
     MachineFunction *MF;
     MachineRegisterInfo *MRI;
     const TargetRegisterInfo *TRI;
     const TargetInstrInfo *TII;
     RegisterClassInfo RegClassInfo;
 
     // Basic block currently being allocated.

lib/CodeGen/RegAllocGreedy.cpp

#endif
   /// obtained from the TargetSubtargetInfo.
   bool EnableLocalReassign;
 
   /// Set of broken hints that may be reconciled later because of eviction.
   SmallSetVector<LiveInterval *, 8> SetOfBrokenHints;
 
 public:
   RAGreedy();
+  SUPPORTS_VIRTUAL_REGISTERS
 
   /// Return the pass name.
   const char* getPassName() const override {
     return "Greedy Register Allocator";
   }
 
   /// RAGreedy analysis usage.
   void getAnalysisUsage(AnalysisUsage &AU) const override;

lib/CodeGen/RegAllocPBQP.cpp

public:
   /// Construct a PBQP register allocator.
   RegAllocPBQP(char *cPassID = nullptr)
       : MachineFunctionPass(ID), customPassID(cPassID) {
     initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
     initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
     initializeLiveStacksPass(*PassRegistry::getPassRegistry());
     initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
   }
+  SUPPORTS_VIRTUAL_REGISTERS
 
   /// Return the pass name.
   const char* getPassName() const override {
     return "PBQP Register Allocator";
   }
 
   /// PBQP analysis usage.
   void getAnalysisUsage(AnalysisUsage &au) const override;

lib/CodeGen/RegisterCoalescer.cpp

void shrinkToUses(LiveInterval *LI,
       }
     }
 
   public:
     static char ID; ///< Class identification, replacement for typeinfo
     RegisterCoalescer() : MachineFunctionPass(ID) {
       initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
     }
+    SUPPORTS_VIRTUAL_REGISTERS
 
     void getAnalysisUsage(AnalysisUsage &AU) const override;
 
     void releaseMemory() override;
 
     /// This is the pass entry point.
     bool runOnMachineFunction(MachineFunction&) override;
 

lib/CodeGen/SpillPlacement.h

class SpillPlacement : public MachineFunctionPass {
   /// its inputs falls in the open interval (-Threshold;Threshold).
   BlockFrequency Threshold;
 
 public:
   static char ID; // Pass identification, replacement for typeid.
 
   SpillPlacement() : MachineFunctionPass(ID), nodes(nullptr) {}
   ~SpillPlacement() override { releaseMemory(); }
+  SUPPORTS_VIRTUAL_REGISTERS
 
   /// BorderConstraint - A basic block has separate constraints for entry and
   /// exit.
   enum BorderConstraint {
     DontCare,  ///< Block doesn't care / variable not live.
     PrefReg,   ///< Block entry/exit prefers a register.
     PrefSpill, ///< Block entry/exit prefers a stack slot.
     PrefBoth,  ///< Block entry prefers both register and stack.

lib/CodeGen/StackColoring.cpp

class StackColoring : public MachineFunctionPass {
   /// once the coloring is done.
   SmallVector<MachineInstr*, 8> Markers;
 
 public:
   static char ID;
   StackColoring() : MachineFunctionPass(ID) {
     initializeStackColoringPass(*PassRegistry::getPassRegistry());
   }
+  SUPPORTS_VIRTUAL_REGISTERS
   void getAnalysisUsage(AnalysisUsage &AU) const override;
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 private:
   /// Debug.
   void dump() const;
 
   /// Removes all of the lifetime marker instructions from the function.

lib/CodeGen/TailDuplication.cpp

class TailDuplicatePass : public MachineFunctionPass {
     bool PreRegAlloc;
 
     // A list of virtual registers for which to update SSA form.
     SmallVector<unsigned, 16> SSAUpdateVRs;
 
     // For each virtual register in SSAUpdateVals keep a list of source virtual
     // registers.
     DenseMap<unsigned, AvailableValsTy> SSAUpdateVals;
-
+    SUPPORTS_VIRTUAL_REGISTERS
   public:
     static char ID;
     explicit TailDuplicatePass() :
       MachineFunctionPass(ID), PreRegAlloc(false) {}
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
     void getAnalysisUsage(AnalysisUsage &AU) const override;

lib/CodeGen/TwoAddressInstructionPass.cpp

class TwoAddressInstructionPass : public MachineFunctionPass {
   void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
   void eliminateRegSequence(MachineBasicBlock::iterator&);
 
 public:
   static char ID; // Pass identification, replacement for typeid
   TwoAddressInstructionPass() : MachineFunctionPass(ID) {
     initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
   }
+  SUPPORTS_VIRTUAL_REGISTERS
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addRequired<AAResultsWrapperPass>();
     AU.addPreserved<LiveVariables>();
     AU.addPreserved<SlotIndexes>();
     AU.addPreserved<LiveIntervals>();
     AU.addPreservedID(MachineLoopInfoID);

lib/CodeGen/UnreachableBlockElim.cpp

 namespace {
   class UnreachableMachineBlockElim : public MachineFunctionPass {
     bool runOnMachineFunction(MachineFunction &F) override;
     void getAnalysisUsage(AnalysisUsage &AU) const override;
     MachineModuleInfo *MMI;
   public:
     static char ID; // Pass identification, replacement for typeid
     UnreachableMachineBlockElim() : MachineFunctionPass(ID) {}
+    SUPPORTS_VIRTUAL_REGISTERS
   };
 }
 char UnreachableMachineBlockElim::ID = 0;
 
 INITIALIZE_PASS(UnreachableMachineBlockElim, "unreachable-mbb-elimination",
   "Remove unreachable machine basic blocks", false, false)
 
 char &llvm::UnreachableMachineBlockElimID = UnreachableMachineBlockElim::ID;

lib/CodeGen/VirtRegMap.cpp

class VirtRegRewriter : public MachineFunctionPass {
   void rewrite();
   void addMBBLiveIns();
   bool readsUndefSubreg(const MachineOperand &MO) const;
   void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
 
 public:
   static char ID;
   VirtRegRewriter() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   bool runOnMachineFunction(MachineFunction&) override;
 };
 } // end anonymous namespace
 
 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
for (MachineBasicBlock::instr_iterator
         if (Indexes)
           Indexes->removeMachineInstrFromMaps(MI);
         // It's safe to erase MI because MII has already been incremented.
         MI->eraseFromParent();
       }
     }
   }
 }
-

lib/Target/WebAssembly/WebAssemblyArgumentMove.cpp

 
 #define DEBUG_TYPE "wasm-argument-move"
 
 namespace {
 class WebAssemblyArgumentMove final : public MachineFunctionPass {
 public:
   static char ID; // Pass identification, replacement for typeid
   WebAssemblyArgumentMove() : MachineFunctionPass(ID) {}
-
+  //virtual bool getSupportsVirtualRegisters() const { return true; }
+  SUPPORTS_VIRTUAL_REGISTERS
   const char *getPassName() const override {
     return "WebAssembly Argument Move";
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addPreserved<MachineBlockFrequencyInfo>();
     AU.addPreservedID(MachineDominatorsID);

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

 
 class WebAssemblyAsmPrinter final : public AsmPrinter {
   const MachineRegisterInfo *MRI;
   const WebAssemblyFunctionInfo *MFI;
 
 public:
   WebAssemblyAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), MRI(nullptr), MFI(nullptr) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 
 private:
   const char *getPassName() const override {
     return "WebAssembly Assembly Printer";
   }
 
   //===------------------------------------------------------------------===//
   // MachineFunctionPass Implementation.

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 public:
   static char ID; // Pass identification, replacement for typeid
   WebAssemblyCFGStackify() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 };
 } // end anonymous namespace
 
 char WebAssemblyCFGStackify::ID = 0;
 FunctionPass *llvm::createWebAssemblyCFGStackify() {
   return new WebAssemblyCFGStackify();
 }
 

lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 public:
   static char ID; // Pass identification, replacement for typeid
   WebAssemblyLowerBrUnless() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 };
 } // end anonymous namespace
 
 char WebAssemblyLowerBrUnless::ID = 0;
 FunctionPass *llvm::createWebAssemblyLowerBrUnless() {
   return new WebAssemblyLowerBrUnless();
 }
 

lib/Target/WebAssembly/WebAssemblyPEI.cpp

 }
 namespace {
 class WasmPEI : public MachineFunctionPass {
 public:
   static char ID;
   WasmPEI() : MachineFunctionPass(ID) {
     initializeWasmPEIPass(*PassRegistry::getPassRegistry());
   }
+  SUPPORTS_VIRTUAL_REGISTERS
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
   /// frame indexes with appropriate references.
   ///
   bool runOnMachineFunction(MachineFunction &Fn) override;
 

lib/Target/WebAssembly/WebAssemblyPeephole.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 public:
   static char ID;
   WebAssemblyPeephole() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 };
 } // end anonymous namespace
 
 char WebAssemblyPeephole::ID = 0;
 FunctionPass *llvm::createWebAssemblyPeephole() {
   return new WebAssemblyPeephole();
 }
 

lib/Target/WebAssembly/WebAssemblyRegColoring.cpp

 
 #define DEBUG_TYPE "wasm-reg-coloring"
 
 namespace {
 class WebAssemblyRegColoring final : public MachineFunctionPass {
 public:
   static char ID; // Pass identification, replacement for typeid
   WebAssemblyRegColoring() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 
   const char *getPassName() const override {
     return "WebAssembly Register Coloring";
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addRequired<LiveIntervals>();

lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 public:
   static char ID; // Pass identification, replacement for typeid
   WebAssemblyRegNumbering() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 };
 } // end anonymous namespace
 
 char WebAssemblyRegNumbering::ID = 0;
 FunctionPass *llvm::createWebAssemblyRegNumbering() {
   return new WebAssemblyRegNumbering();
 }
 

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

void getAnalysisUsage(AnalysisUsage &AU) const override {
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 public:
   static char ID; // Pass identification, replacement for typeid
   WebAssemblyRegStackify() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 };
 } // end anonymous namespace
 
 char WebAssemblyRegStackify::ID = 0;
 FunctionPass *llvm::createWebAssemblyRegStackify() {
   return new WebAssemblyRegStackify();
 }
 

lib/Target/WebAssembly/WebAssemblyStoreResults.cpp

 
 #define DEBUG_TYPE "wasm-store-results"
 
 namespace {
 class WebAssemblyStoreResults final : public MachineFunctionPass {
 public:
   static char ID; // Pass identification, replacement for typeid
   WebAssemblyStoreResults() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 
   const char *getPassName() const override {
     return "WebAssembly Store Results";
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addRequired<MachineBlockFrequencyInfo>();

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

public:
 
   FunctionPass *createTargetRegisterAllocator(bool) override;
 
   void addIRPasses() override;
   bool addInstSelector() override;
   bool addILPOpts() override;
   void addPreRegAlloc() override;
   void addPostRegAlloc() override;
+  void addMachineLateOptimization() override;
+  bool addGCPasses() override { return false; }
   void addPreEmitPass() override;
 };
 } // end anonymous namespace
 
 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() {
   return TargetIRAnalysis([this](const Function &F) {
     return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
   });
if (getOptLevel() != CodeGenOpt::None)
     addPass(createWebAssemblyStoreResults());
 }
 
 void WebAssemblyPassConfig::addPostRegAlloc() {
   // TODO: The following CodeGen passes don't currently support code containing
   // virtual registers. Consider removing their restrictions and re-enabling
   // them.
   //
+
+  // Has no asserts of its own, but was not written to handle virtual regs.
+  disablePass(&ShrinkWrapID);
   // We use our own PrologEpilogInserter which is very slightly modified to
   // tolerate virtual registers.
   disablePass(&PrologEpilogCodeInserterID);
   // Fails with: should be run after register allocation.
   disablePass(&MachineCopyPropagationID);
 
   // Mark registers as representing wasm's expression stack.
   addPass(createWebAssemblyRegStackify());
 
   // Run the register coloring pass to reduce the total number of registers.
   addPass(createWebAssemblyRegColoring());
 
   TargetPassConfig::addPostRegAlloc();
 
   // Run WebAssembly's version of the PrologEpilogInserter. Target-independent
   // PEI runs after PostRegAlloc and after ShrinkWrap. Putting it here will run
   // PEI before ShrinkWrap but otherwise in the same position in the order.
   addPass(createWebAssemblyPEI());
 }
 
+void WebAssemblyPassConfig::addMachineLateOptimization() {
+  disablePass(&MachineCopyPropagationID);
+  disablePass(&PostRASchedulerID);
+  TargetPassConfig::addMachineLateOptimization();
+}
+
 void WebAssemblyPassConfig::addPreEmitPass() {
   TargetPassConfig::addPreEmitPass();
 
+  disablePass(&FuncletLayoutID);
+  disablePass(&StackMapLivenessID);
+  disablePass(&LiveDebugValuesID);
+
   // Put the CFG in structured form; insert BLOCK and LOOP markers.
   addPass(createWebAssemblyCFGStackify());
 
   // Lower br_unless into br_if.
   addPass(createWebAssemblyLowerBrUnless());
 
   // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
   addPass(createWebAssemblyRegNumbering());
 
   // Perform the very last peephole optimizations on the code.
   if (getOptLevel() != CodeGenOpt::None)
     addPass(createWebAssemblyPeephole());
 }

lib/Target/X86/X86CallFrameOptimization.cpp

static cl::opt<bool>
     NoX86CFOpt("no-x86-call-frame-opt",
                cl::desc("Avoid optimizing x86 call frames for size"),
                cl::init(false), cl::Hidden);
 
 namespace {
 class X86CallFrameOptimization : public MachineFunctionPass {
 public:
   X86CallFrameOptimization() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
 private:
   // Information we know about a particular call site
   struct CallContext {
     CallContext()
         : FrameSetup(nullptr), Call(nullptr), SPCopy(nullptr), ExpectedDist(0),

lib/Target/X86/X86InstrInfo.cpp

 }
 
 namespace {
   /// Create Global Base Reg pass. This initializes the PIC
   /// global base register for x86-32.
   struct CGBR : public MachineFunctionPass {
     static char ID;
     CGBR() : MachineFunctionPass(ID) {}
+    SUPPORTS_VIRTUAL_REGISTERS
 
     bool runOnMachineFunction(MachineFunction &MF) override {
       const X86TargetMachine *TM =
         static_cast<const X86TargetMachine *>(&MF.getTarget());
       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
 
       // Don't do anything if this is 64-bit as 64-bit PIC
       // uses RIP relative addressing.

 char CGBR::ID = 0;
 FunctionPass*
 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
 
 namespace {
   struct LDTLSCleanup : public MachineFunctionPass {
     static char ID;
     LDTLSCleanup() : MachineFunctionPass(ID) {}
+    SUPPORTS_VIRTUAL_REGISTERS
 
     bool runOnMachineFunction(MachineFunction &MF) override {
       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
         // No point folding accesses if there isn't at least two.
         return false;
       }
 

lib/Target/X86/X86OptimizeLEAs.cpp

 
 STATISTIC(NumSubstLEAs, "Number of LEA instruction substitutions");
 STATISTIC(NumRedundantLEAs, "Number of redundant LEA instructions removed");
 
 namespace {
 class OptimizeLEAPass : public MachineFunctionPass {
 public:
   OptimizeLEAPass() : MachineFunctionPass(ID) {}
+  SUPPORTS_VIRTUAL_REGISTERS
 
   const char *getPassName() const override { return "X86 LEA Optimize"; }
 
   /// \brief Loop over all of the basic blocks, replacing address
   /// calculations in load and store instructions, if it's already
   /// been calculated by LEA. Also, remove redundant LEAs.
   bool runOnMachineFunction(MachineFunction &MF) override;