Split PrologEpilogInserter into 2 parts

[dschuff]

Summary

The base part finalizes frame layout, inserts prolog/epilog code, and
eliminates FrameIndex operands. It supports virtual registers but does not
support callee-saved registers or scavenging
The CSR-supporting part handles spilling of callee-saved registers and
scavenging, but does not support virtual registers.

[hfinkel]

lib/CodeGen/PrologEpilogInserter.cpp

264

Did we decide that we need to split the passes this way? It seems like the boilerplate from having two passes seems >= the difference between this runOnMachineFunction implementation and the simpler version.

356

Does having > INT_MAX FIs really work with just these changes?

[dschuff]

lib/CodeGen/PrologEpilogInserter.cpp

264

The motivation for this change was the really strong desire expressed to have clear separation at the pass level between passes that support virtual registers and passes that do not. (see also http://reviews.llvm.org/D16483). If we implement that, then we have to have a PEI pass that supports virtual registers.

Of course we could just declare that this PEI pass supports virtual registers. From my own experience and auditing of the code, it seems to work fine for WebAssembly. The subsets that WebAssembly uses (i.e. the parts that I've broken out here into the base PEI) are the only parts that actually run when the target returns an empty set of CSRs; I've basically just made that distinction explicit in this change. I'd be interested in getting an opinion from @qcolombet based on this more concrete change.

356

No, this change was just to make the types (signed vs unsigned) consistent (see also line 664 below), and, if there's going to be a sentinel value, it might as well be the max for the actual type used (unsigned) instead of a different type.

[qcolombet]

Hi Derek,

I am behind on reviews and I am still fighting to catching up.
I have one high level comment though, see the inlined comment.

Cheers,
-Quentin

lib/CodeGen/PrologEpilogInserter.cpp

77

It feels wrong to me that the high level class needs to have this field.

[dschuff]

lib/CodeGen/PrologEpilogInserter.cpp

77

I kind of agree. There are a couple of reasons:

1. TargetFrameLowering::processFunctionBeforeFrameFinalized() is called by the base PEI::finalizeFrame() and it takes an RS pointer because this is the point where targets (PPC) create a stack slot for the RS to spill into. We could maybe work around that by adding a virtual method on the base class that calls processFunctionBeforeFrameFinalized() with a nullptr and with the real RS in the derived class.
2. The base PEI::calculateFrameObjectOffsets() takes the scavenging spill slots into account when it lays out the stack frame, and uses the RS to find out where they are. (Likewise it also handles the CSR spill slots, which in principle the base class doesn't need to do). This seems trickier to work around. We could move the code that actually uses RS out to some other function but the logic of where it goes in the frame would still be local.
3. The base PEI::replaceFrameIndices() keeps the RS up to date as it goes and passes RS to TargetRegisterInfo::eliminateFrameIndex() which is of course where it might actually be wanted by a target.

The root sources of this are that the stack frame layout (which is implemented in this pass, and is always needed) has to be aware of both CSRs and scavenging; and the target hooks (which are also always used) might need RS in any case.
We could try to move the RS/CSR frame layout code and the RS updating code out into some kind of other abstraction, but the RS class is itself essentially the abstraction that you'd want.

[dschuff]

Another option might be to use a similar factoring (which splits the code that must deal with virtual registers out from the code that need not), but not actually create 2 different MachineFunctionPasses. We could say that the pass itself supports virtual registers, but we'd have better organization and clearer separation.

[qcolombet]

Hi Derek,

Another option might be to use a similar factoring (which splits the code that must deal with virtual registers out from the code that need not), but not actually create 2 different MachineFunctionPasses. We could say that the pass itself supports virtual registers, but we'd have better organization and clearer separation.

This may be the cleanest solution.

Could you prepare a patch for that direction?

Thanks,
-Quentin

[dschuff]

http://reviews.llvm.org/D18366 has a change to tweak the organization and naming in PEI, with better-targeted asserts. We could also go a bit further and split the calls that are currently in runOnMachineFunction into different functions the way we have e.g. finalizeframe() here.

[dschuff]

Abandoned in favor of http://reviews.llvm.org/D18366

include/llvm/CodeGen/Passes.h

/// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
   /// Quadratic Prograaming (PBQP) based register allocator.
   ///
   FunctionPass *createDefaultPBQPRegisterAllocator();
 
   /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
   /// and eliminates abstract frame references.
   extern char &PrologEpilogCodeInserterID;
 
+  /// Prolog/Epilog inserter without CSRs - A version of PEI that does not use
+  /// or support callee-saved registers or scavenging, but does support use of
+  /// virtual registers instead of only physical registers. Targets can
+  /// substitute it for the default PrologEpilogCodeInserterID.
+  extern char &VRegPrologEpilogCodeInserterID;
+
   /// ExpandPostRAPseudos - This pass expands pseudo instructions after
   /// register allocation.
   extern char &ExpandPostRAPseudosID;
 
   /// createPostRAScheduler - This pass performs post register allocation
   /// scheduling.
   extern char &PostRASchedulerID;
 

include/llvm/InitializePasses.h

 void initializeObjCARCAPElimPass(PassRegistry&);
 void initializeObjCARCExpandPass(PassRegistry&);
 void initializeObjCARCContractPass(PassRegistry&);
 void initializeObjCARCOptPass(PassRegistry&);
 void initializePAEvalPass(PassRegistry &);
 void initializeOptimizePHIsPass(PassRegistry&);
 void initializePartiallyInlineLibCallsPass(PassRegistry&);
 void initializePEIPass(PassRegistry&);
+void initializePEIWithCSRsPass(PassRegistry&);
 void initializePHIEliminationPass(PassRegistry&);
 void initializePartialInlinerPass(PassRegistry&);
 void initializePeepholeOptimizerPass(PassRegistry&);
 void initializePostDomOnlyPrinterPass(PassRegistry&);
 void initializePostDomOnlyViewerPass(PassRegistry&);
 void initializePostDomPrinterPass(PassRegistry&);
 void initializePostDomViewerPass(PassRegistry&);
 void initializePostDominatorTreePass(PassRegistry&);

lib/CodeGen/CodeGen.cpp

void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeMachineLoopInfoPass(Registry);
   initializeMachineModuleInfoPass(Registry);
   initializeMachinePostDominatorTreePass(Registry);
   initializeMachineSchedulerPass(Registry);
   initializeMachineSinkingPass(Registry);
   initializeMachineVerifierPassPass(Registry);
   initializeOptimizePHIsPass(Registry);
   initializePEIPass(Registry);
+  initializePEIWithCSRsPass(Registry);
   initializePHIEliminationPass(Registry);
   initializePeepholeOptimizerPass(Registry);
   initializePostMachineSchedulerPass(Registry);
   initializePostRASchedulerPass(Registry);
   initializeProcessImplicitDefsPass(Registry);
   initializeRegisterCoalescerPass(Registry);
   initializeShrinkWrapPass(Registry);
   initializeSlotIndexesPass(Registry);

lib/CodeGen/PrologEpilogInserter.cpp

 #include "llvm/Target/TargetSubtargetInfo.h"
 #include <climits>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "pei"
 
 namespace {
+// The PrologEpilogInserter base class performs frame finalization,
+// prolog/epilog code insertion, and FrameIndex elimination. It does not handle
+// callee-saved registers or scavenging, but it does support virtual registers
+// (i.e. it is suitable for virtual targets which do not use a register
+// allocator)
 class PEI : public MachineFunctionPass {
 public:
   static char ID;
-  PEI() : MachineFunctionPass(ID) {
-    initializePEIPass(*PassRegistry::getPassRegistry());
-  }
+  PEI() : PEI(ID) { initializePEIPass(*PassRegistry::getPassRegistry()); }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
   /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
   /// frame indexes with appropriate references.
   ///
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
-private:
-  RegScavenger *RS;
+ protected:
+  PEI(char &SubclassID) : MachineFunctionPass(SubclassID) {}
+
+  // Register scavenging is only supported in PEIWithCSRs and not in the base
+  // class. However, an RS pointer (possibly null) must be passed to several
+  // of the target hooks used in the base class and the logic for FI
+  // replacement sometimes depends on it.
+  RegScavenger *RS = nullptr;
+
+  // Flag to control whether to use the register scavenger to resolve
+  // frame index materialization registers. Set according to
+  // TRI->requiresFrameIndexScavenging() for the current function.
+  bool FrameIndexVirtualScavenging = false;
 
   // MinCSFrameIndex, MaxCSFrameIndex - Keeps the range of callee saved
   // stack frame indexes.
-  unsigned MinCSFrameIndex, MaxCSFrameIndex;
+  unsigned MinCSFrameIndex = std::numeric_limits<unsigned>::max();
+  unsigned MaxCSFrameIndex = 0;
 
   // Save and Restore blocks of the current function. Typically there is a
   // single save block, unless Windows EH funclets are involved.
   SmallVector<MachineBasicBlock *, 1> SaveBlocks;
   SmallVector<MachineBasicBlock *, 4> RestoreBlocks;
 
-  // Flag to control whether to use the register scavenger to resolve
-  // frame index materialization registers. Set according to
-  // TRI->requiresFrameIndexScavenging() for the current function.
-  bool FrameIndexVirtualScavenging;
-
+  void init(MachineFunction &Fn);
   void calculateSets(MachineFunction &Fn);
   void calculateCallsInformation(MachineFunction &Fn);
-  void assignCalleeSavedSpillSlots(MachineFunction &Fn,
-                                   const BitVector &SavedRegs);
-  void insertCSRSpillsAndRestores(MachineFunction &Fn);
+
+  void finalizeFrame(MachineFunction &Fn);
   void calculateFrameObjectOffsets(MachineFunction &Fn);
   void replaceFrameIndices(MachineFunction &Fn);
   void replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
                            int &SPAdj);
-  void scavengeFrameVirtualRegs(MachineFunction &Fn);
+
   void insertPrologEpilogCode(MachineFunction &Fn);
 };
+
+class PEIWithCSRs : public PEI {
+ public:
+  static char ID;
+  PEIWithCSRs() : PEI(ID) {
+    initializePEIWithCSRsPass(*PassRegistry::getPassRegistry());
+  }
+  /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
+  /// frame indexes with appropriate references.
+  ///
+  bool runOnMachineFunction(MachineFunction &Fn) override;
+
+ private:
+  void assignCalleeSavedSpillSlots(MachineFunction &Fn,
+                                   const BitVector &SavedRegs);
+  void insertCSRSpillsAndRestores(MachineFunction &Fn);
+  void scavengeFrameVirtualRegs(MachineFunction &Fn);
+};
 } // namespace
 
 char PEI::ID = 0;
-char &llvm::PrologEpilogCodeInserterID = PEI::ID;
+char PEIWithCSRs::ID = 0;
+char &llvm::PrologEpilogCodeInserterID = PEIWithCSRs::ID;
+char &llvm::VRegPrologEpilogCodeInserterID = PEI::ID;
 
 static cl::opt<unsigned>
 WarnStackSize("warn-stack-size", cl::Hidden, cl::init((unsigned)-1),
               cl::desc("Warn for stack size bigger than the given"
                        " number"));
 
-INITIALIZE_PASS_BEGIN(PEI, "prologepilog",
+INITIALIZE_PASS_BEGIN(PEI, "prologepilog-no-csrs",
+                      "Prologue/Epilogue Insertion (no CSRs)", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
+INITIALIZE_PASS_DEPENDENCY(StackProtector)
+INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
+INITIALIZE_PASS_END(
+    PEI, "prologepilog-no-csrs",
+    "Prologue/Epilogue Insertion & Frame Finalization (no CSRs)", false, false)
+
+INITIALIZE_PASS_BEGIN(PEIWithCSRs, "prologepilog",
                       "Prologue/Epilogue Insertion", false, false)
 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
 INITIALIZE_PASS_DEPENDENCY(StackProtector)
 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
-INITIALIZE_PASS_END(PEI, "prologepilog",
-                    "Prologue/Epilogue Insertion & Frame Finalization",
-                    false, false)
+INITIALIZE_PASS_END(PEIWithCSRs, "prologepilog",
+                    "Prologue/Epilogue Insertion & Frame Finalization", false,
+                    false)
 
 STATISTIC(NumScavengedRegs, "Number of frame index regs scavenged");
 STATISTIC(NumBytesStackSpace,
           "Number of bytes used for stack in all functions");
 
 void PEI::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.setPreservesCFG();
   AU.addPreserved<MachineLoopInfo>();
for (MachineBasicBlock &MBB : Fn) {
     if (MBB.isReturnBlock())
       RestoreBlocks.push_back(&MBB);
   }
 }
 
 /// StackObjSet - A set of stack object indexes
 typedef SmallSetVector<int, 8> StackObjSet;
 
-/// runOnMachineFunction - Insert prolog/epilog code and replace abstract
-/// frame indexes with appropriate references.
-///
-bool PEI::runOnMachineFunction(MachineFunction &Fn) {
-  const Function* F = Fn.getFunction();
-  const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
-  const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
-
-  assert(!Fn.getRegInfo().getNumVirtRegs() && "Regalloc must assign all vregs");
-
-  RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : nullptr;
-  FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn);
-
+void PEI::init(MachineFunction &Fn) {
   // Calculate the MaxCallFrameSize and AdjustsStack variables for the
   // function's frame information. Also eliminates call frame pseudo
   // instructions.
   calculateCallsInformation(Fn);
 
-  // Determine which of the registers in the callee save list should be saved.
-  BitVector SavedRegs;
-  TFI->determineCalleeSaves(Fn, SavedRegs, RS);
-
-  // Insert spill code for any callee saved registers that are modified.
-  assignCalleeSavedSpillSlots(Fn, SavedRegs);
-
   // Determine placement of CSR spill/restore code:
   // place all spills in the entry block, all restores in return blocks.
   calculateSets(Fn);
+}
 
-  // Add the code to save and restore the callee saved registers.
-  if (!F->hasFnAttribute(Attribute::Naked))
-    insertCSRSpillsAndRestores(Fn);
+/// runOnMachineFunction - Insert prolog/epilog code and replace abstract
+/// frame indexes with appropriate references.
+///
+bool PEI::runOnMachineFunction(MachineFunction &Fn) {
+  assert(!RS && "Base PEI does not support scavenging");
+
+  init(Fn);
+  finalizeFrame(Fn);
+
+  return true;
+}
+
+/// Finalize the frame layout, insert prolog and epilog code, and replace
+/// FrameIndex operands.
+void PEI::finalizeFrame(MachineFunction &Fn) {
+  const Function *F = Fn.getFunction();
+  const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
 
   // Allow the target machine to make final modifications to the function
   // before the frame layout is finalized.
   TFI->processFunctionBeforeFrameFinalized(Fn, RS);
 
   // Calculate actual frame offsets for all abstract stack objects...
   calculateFrameObjectOffsets(Fn);
 
   // Add prolog and epilog code to the function.  This function is required
   // to align the stack frame as necessary for any stack variables or
   // called functions.  Because of this, calculateCalleeSavedRegisters()
   // must be called before this function in order to set the AdjustsStack
   // and MaxCallFrameSize variables.
   if (!F->hasFnAttribute(Attribute::Naked))
     insertPrologEpilogCode(Fn);
 
   // Replace all MO_FrameIndex operands with physical register references
   // and actual offsets.
   //
   replaceFrameIndices(Fn);
 
-  // If register scavenging is needed, as we've enabled doing it as a
-  // post-pass, scavenge the virtual registers that frame index elimination
-  // inserted.
-  if (TRI->requiresRegisterScavenging(Fn) && FrameIndexVirtualScavenging)
-    scavengeFrameVirtualRegs(Fn);
-
-  // Clear any vregs created by virtual scavenging.
-  Fn.getRegInfo().clearVirtRegs();
-
   // Warn on stack size when we exceeds the given limit.
   MachineFrameInfo *MFI = Fn.getFrameInfo();
   uint64_t StackSize = MFI->getStackSize();
   if (WarnStackSize.getNumOccurrences() > 0 && WarnStackSize < StackSize) {
     DiagnosticInfoStackSize DiagStackSize(*F, StackSize);
     F->getContext().diagnose(DiagStackSize);
   }
 
-  delete RS;
   SaveBlocks.clear();
   RestoreBlocks.clear();
+}
+
+bool PEIWithCSRs::runOnMachineFunction(MachineFunction &Fn) {
+  const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
+  const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
+  RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : nullptr;
+  FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn);
+
+  assert(!Fn.getRegInfo().getNumVirtRegs() && "Regalloc must assign all vregs");
+
+  init(Fn);
+
+  // Determine which of the registers in the callee save list should be saved.
+  BitVector SavedRegs;
+  TFI->determineCalleeSaves(Fn, SavedRegs, RS);
+
+  // Assign stack slots for any callee-saved registers that must be spilled.
+  assignCalleeSavedSpillSlots(Fn, SavedRegs);
+
+  // Add the code to save and restore the callee saved registers.
+  if (!Fn.getFunction()->hasFnAttribute(Attribute::Naked))
+    insertCSRSpillsAndRestores(Fn);
+
+  finalizeFrame(Fn);
+
+  // If register scavenging is needed, as we've enabled doing it as a
+  // post-pass, scavenge the virtual registers that frame index elimination
+  // inserted.
+  if (RS && FrameIndexVirtualScavenging) scavengeFrameVirtualRegs(Fn);
+
+  // Clear any vregs created by virtual scavenging.
+  Fn.getRegInfo().clearVirtRegs();
+
+  delete RS;
   return true;
 }
 
 /// calculateCallsInformation - Calculate the MaxCallFrameSize and AdjustsStack
 /// variables for the function's frame information and eliminate call frame
 /// pseudo instructions.
 void PEI::calculateCallsInformation(MachineFunction &Fn) {
   const TargetInstrInfo &TII = *Fn.getSubtarget().getInstrInfo();
for (std::vector<MachineBasicBlock::iterator>::iterator
     // the target doesn't indicate otherwise, remove the call frame pseudos
     // here. The sub/add sp instruction pairs are still inserted, but we don't
     // need to track the SP adjustment for frame index elimination.
     if (TFI->canSimplifyCallFramePseudos(Fn))
       TFI->eliminateCallFramePseudoInstr(Fn, *I->getParent(), I);
   }
 }
 
-void PEI::assignCalleeSavedSpillSlots(MachineFunction &F,
+void PEIWithCSRs::assignCalleeSavedSpillSlots(MachineFunction &F,
                                               const BitVector &SavedRegs) {
   // These are used to keep track the callee-save area. Initialize them.
-  MinCSFrameIndex = INT_MAX;
+  MinCSFrameIndex = std::numeric_limits<unsigned>::max();
   MaxCSFrameIndex = 0;
 
   if (SavedRegs.empty())
     return;
 
   const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo();
   const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F);
 
for (MachineBasicBlock *MBB : Visited) {
         MBB->addLiveIn(Reg);
     }
   }
 }
 
 /// insertCSRSpillsAndRestores - Insert spill and restore code for
 /// callee saved registers used in the function.
 ///
-void PEI::insertCSRSpillsAndRestores(MachineFunction &Fn) {
+void PEIWithCSRs::insertCSRSpillsAndRestores(MachineFunction &Fn) {
   // Get callee saved register information.
   MachineFrameInfo *MFI = Fn.getFrameInfo();
   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
 
   MFI->setCalleeSavedInfoValid(true);
 
   // Early exit if no callee saved registers are modified!
   if (CSI.empty())
for (unsigned i = MinCSFrameIndex; i <= MaxCSFrameIndex; ++i) {
 
       unsigned Align = MFI->getObjectAlignment(i);
       // Adjust to alignment boundary
       Offset = alignTo(Offset, Align, Skew);
 
       MFI->setObjectOffset(i, -Offset);        // Set the computed offset
     }
   } else {
-    int MaxCSFI = MaxCSFrameIndex, MinCSFI = MinCSFrameIndex;
-    for (int i = MaxCSFI; i >= MinCSFI ; --i) {
+    unsigned MaxCSFI = MaxCSFrameIndex, MinCSFI = MinCSFrameIndex;
+    for (unsigned i = MaxCSFI; i >= MinCSFI; --i) {
       unsigned Align = MFI->getObjectAlignment(i);
       // Adjust to alignment boundary
       Offset = alignTo(Offset, Align, Skew);
 
       MFI->setObjectOffset(i, Offset);
       Offset += MFI->getObjectSize(i);
     }
   }

 
 /// scavengeFrameVirtualRegs - Replace all frame index virtual registers
 /// with physical registers. Use the register scavenger to find an
 /// appropriate register to use.
 ///
 /// FIXME: Iterating over the instruction stream is unnecessary. We can simply
 /// iterate over the vreg use list, which at this point only contains machine
 /// operands for which eliminateFrameIndex need a new scratch reg.
-void
-PEI::scavengeFrameVirtualRegs(MachineFunction &Fn) {
+void PEIWithCSRs::scavengeFrameVirtualRegs(MachineFunction &Fn) {
   // Run through the instructions and find any virtual registers.
   for (MachineFunction::iterator BB = Fn.begin(),
        E = Fn.end(); BB != E; ++BB) {
     RS->enterBasicBlock(&*BB);
 
     int SPAdj = 0;
 
     // The instruction stream may change in the loop, so check BB->end()
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) {
           unsigned ScratchReg = RS->scavengeRegister(RC, J, SPAdj);
 
           ++NumScavengedRegs;
 
           // Replace this reference to the virtual register with the
           // scratch register.
           assert (ScratchReg && "Missing scratch register!");
           Fn.getRegInfo().replaceRegWith(Reg, ScratchReg);
-          
           // Because this instruction was processed by the RS before this
           // register was allocated, make sure that the RS now records the
           // register as being used.
           RS->setRegUsed(ScratchReg);
         }
       }
 
       // If the scavenger needed to use one of its spill slots, the

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

void WebAssemblyPassConfig::addPreRegAlloc() {
   if (getOptLevel() != CodeGenOpt::None)
     addPass(createWebAssemblyStoreResults());
 }
 
 void WebAssemblyPassConfig::addPostRegAlloc() {
   // TODO: The following CodeGen passes don't currently support code containing
   // virtual registers. Consider removing their restrictions and re-enabling
   // them.
-  //
-  // We use our own PrologEpilogInserter which is very slightly modified to
-  // tolerate virtual registers.
-  disablePass(&PrologEpilogCodeInserterID);
+
+  // Use the VReg version of PrologEpilogInserter which doesn't support CSRs
+  // but does support virtual registers.
+  // TODO: Delete WebAssemblyPEI code.
+  substitutePass(&PrologEpilogCodeInserterID, &VRegPrologEpilogCodeInserterID);
   // Fails with: should be run after register allocation.
   disablePass(&MachineCopyPropagationID);
 
   // Mark registers as representing wasm's expression stack.
   addPass(createWebAssemblyRegStackify());
 
   // Run the register coloring pass to reduce the total number of registers.
   addPass(createWebAssemblyRegColoring());
 
   TargetPassConfig::addPostRegAlloc();
-
-  // Run WebAssembly's version of the PrologEpilogInserter. Target-independent
-  // PEI runs after PostRegAlloc and after ShrinkWrap. Putting it here will run
-  // PEI before ShrinkWrap but otherwise in the same position in the order.
-  addPass(createWebAssemblyPEI());
 }
 
 void WebAssemblyPassConfig::addPreEmitPass() {
   TargetPassConfig::addPreEmitPass();
 
   // Put the CFG in structured form; insert BLOCK and LOOP markers.
   addPass(createWebAssemblyCFGStackify());