This is an archive of the discontinued LLVM Phabricator instance.

Differential D16462

AMDGPU: Remove Feature64BitPtr
ClosedPublic

Authored by arsenm on Jan 22 2016, 3:38 AM.

Details

Reviewers
• tstellarAMD
Summary

This is a leftover from AMDIL that doesn't do anything
and doesn't belong here.

Diff Detail

Event Timeline

arsenm updated this revision to Diff 45677.Jan 22 2016, 3:38 AM
arsenm retitled this revision from to AMDGPU: Remove Feature64BitPtr.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptJan 22 2016, 3:38 AM
• tstellarAMD accepted this revision.Jan 22 2016, 7:43 AM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Jan 22 2016, 7:43 AM
arsenm closed this revision.Jan 22 2016, 9:36 PM

r258606

Revision Contents

PathSize
lib/
Target/
AMDGPU/
12 lines
5 lines
2 lines

Diff 45677

lib/Target/AMDGPU/AMDGPU.td

Show All 25 Lines
>; >;
def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops", def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
"HalfRate64Ops", "HalfRate64Ops",
"true", "true",
"Most fp64 instructions are half rate instead of quarter" "Most fp64 instructions are half rate instead of quarter"
>; >;
def Feature64BitPtr : SubtargetFeature<"64BitPtr",
"Is64bit",
"true",
"Specify if 64-bit addressing should be used"
>;
def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst", def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
"R600ALUInst", "R600ALUInst",
"false", "false",
"Older version of ALU instructions encoding" "Older version of ALU instructions encoding"
>; >;
def FeatureVertexCache : SubtargetFeature<"HasVertexCache", def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
"HasVertexCache", "HasVertexCache",
▲ Show 20 Lines • Show All 229 Lines • ▼ Show 20 Lines
>; >;
def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS", def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
[FeatureFetchLimit16, FeatureWavefrontSize64, [FeatureFetchLimit16, FeatureWavefrontSize64,
FeatureLocalMemorySize32768] FeatureLocalMemorySize32768]
>; >;
def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS", def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768, [FeatureFP64, FeatureLocalMemorySize32768,
FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding, FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
FeatureLDSBankCount32] FeatureLDSBankCount32]
>; >;
def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS", def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536, [FeatureFP64, FeatureLocalMemorySize65536,
FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace, FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
FeatureGCN1Encoding, FeatureCIInsts] FeatureGCN1Encoding, FeatureCIInsts]
>; >;
def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS", def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
[Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536, [FeatureFP64, FeatureLocalMemorySize65536,
FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN, FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32] FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]
>; >;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def AMDGPUInstrInfo : InstrInfo { def AMDGPUInstrInfo : InstrInfo {
let guessInstructionProperties = 1; let guessInstructionProperties = 1;
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPUSubtarget.h

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines enum {
ISAVersion7_0_1, ISAVersion7_0_1,
ISAVersion8_0_0, ISAVersion8_0_0,
ISAVersion8_0_1, ISAVersion8_0_1,
ISAVersion8_0_3 ISAVersion8_0_3
}; };
private: private:
std::string DevName; std::string DevName;
bool Is64bit;
bool DumpCode; bool DumpCode;
bool R600ALUInst; bool R600ALUInst;
bool HasVertexCache; bool HasVertexCache;
short TexVTXClauseSize; short TexVTXClauseSize;
Generation Gen; Generation Gen;
bool FP64; bool FP64;
bool FP64Denormals; bool FP64Denormals;
bool FP32Denormals; bool FP32Denormals;
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines AMDGPUTargetLowering *getTargetLowering() const override {
return TLInfo.get(); return TLInfo.get();
} }
const InstrItineraryData *getInstrItineraryData() const override { const InstrItineraryData *getInstrItineraryData() const override {
return &InstrItins; return &InstrItins;
} }
void ParseSubtargetFeatures(StringRef CPU, StringRef FS); void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool is64bit() const {
return Is64bit;
}
bool hasVertexCache() const { bool hasVertexCache() const {
return HasVertexCache; return HasVertexCache;
} }
short getTexVTXClauseSize() const { short getTexVTXClauseSize() const {
return TexVTXClauseSize; return TexVTXClauseSize;
} }
▲ Show 20 Lines • Show All 196 Lines • Show Last 20 Lines

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
FP32Denormals = false; FP32Denormals = false;
FP64Denormals = false; FP64Denormals = false;
} }
return *this; return *this;
} }
AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS, AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
TargetMachine &TM) TargetMachine &TM)
: AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false), : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU),
DumpCode(false), R600ALUInst(false), HasVertexCache(false), DumpCode(false), R600ALUInst(false), HasVertexCache(false),
TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false), TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
FP64Denormals(false), FP32Denormals(false), FastFMAF32(false), FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
HalfRate64Ops(false), CaymanISA(false), FlatAddressSpace(false), HalfRate64Ops(false), CaymanISA(false), FlatAddressSpace(false),
FlatForGlobal(false), EnableIRStructurizer(true), FlatForGlobal(false), EnableIRStructurizer(true),
EnablePromoteAlloca(false), EnablePromoteAlloca(false),
EnableIfCvt(true), EnableLoadStoreOpt(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
EnableUnsafeDSOffsetFolding(false), EnableUnsafeDSOffsetFolding(false),
▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines