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Differential D16459

AMDGPU: Don't use separate mulhu/mulhs Pats
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Authored by arsenm on Jan 22 2016, 2:09 AM.

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• tstellarAMD

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arsenm updated this revision to Diff 45669.Jan 22 2016, 2:09 AM

arsenm retitled this revision from to AMDGPU: Don't use separate mulhu/mulhs Pats.

arsenm updated this object.

arsenm added a reviewer: • tstellarAMD.

arsenm added a subscriber: llvm-commits.

Herald added a subscriber: arsenm. · View Herald TranscriptJan 22 2016, 2:09 AM

LGTM.

This revision is now accepted and ready to land.Jan 22 2016, 7:43 AM

r258515

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lib/

Target/

AMDGPU/

SIInstructions.td

14 lines

Diff 45669

lib/Target/AMDGPU/SIInstructions.td

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	} // let SchedRW = [WriteDoubleAdd]			} // let SchedRW = [WriteDoubleAdd]

	let isCommutable = 1, SchedRW = [WriteQuarterRate32] in {			let isCommutable = 1, SchedRW = [WriteQuarterRate32] in {

	defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32",			defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32",
	VOP_I32_I32_I32			VOP_I32_I32_I32
	>;			>;
	defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32",			defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32",
	VOP_I32_I32_I32			VOP_I32_I32_I32, mulhu
	>;			>;

	defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",			defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",
	VOP_I32_I32_I32			VOP_I32_I32_I32
	>;			>;
	defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",			defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
	VOP_I32_I32_I32			VOP_I32_I32_I32, mulhs
	>;			>;

	} // isCommutable = 1, SchedRW = [WriteQuarterRate32]			} // isCommutable = 1, SchedRW = [WriteQuarterRate32]

	let SchedRW = [WriteFloatFMA, WriteSALU] in {			let SchedRW = [WriteFloatFMA, WriteSALU] in {
	defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32",			defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32",
	VOP3b_F32_I1_F32_F32_F32			VOP3b_F32_I1_F32_F32_F32
	>;			>;
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	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//
	// VOP3 Patterns			// VOP3 Patterns
	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//

	def : IMad24Pat<V_MAD_I32_I24>;			def : IMad24Pat<V_MAD_I32_I24>;
	def : UMad24Pat<V_MAD_U32_U24>;			def : UMad24Pat<V_MAD_U32_U24>;

	def : Pat <
	(mulhu i32:$src0, i32:$src1),
	(V_MUL_HI_U32 $src0, $src1)
	>;

	def : Pat <
	(mulhs i32:$src0, i32:$src1),
	(V_MUL_HI_I32 $src0, $src1)
	>;

	defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;			defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
	def : ROTRPattern <V_ALIGNBIT_B32>;			def : ROTRPattern <V_ALIGNBIT_B32>;

	/******** ======================= ********/			/******** ======================= ********/
	/******** Load/Store Patterns ********/			/******** Load/Store Patterns ********/
	/******** ======================= ********/			/******** ======================= ********/

	class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <			class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
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