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Differential D16451

AMDGPU: Remove random TGSI intrinsic
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Authored by arsenm on Jan 21 2016, 11:13 PM.

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Reviewers
• tstellarAMD
Summary

I don't think this was ever used.

Diff Detail

Event Timeline

arsenm updated this revision to Diff 45653.Jan 21 2016, 11:13 PM
arsenm retitled this revision from to AMDGPU: Remove random TGSI intrinsic.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptJan 21 2016, 11:13 PM
• tstellarAMD accepted this revision.Jan 22 2016, 7:40 AM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Jan 22 2016, 7:40 AM
arsenm closed this revision.Jan 22 2016, 10:49 AM

r258514

Revision Contents

PathSize
lib/
Target/
AMDGPU/
5 lines
2 lines
7 lines

Diff 45653

lib/Target/AMDGPU/AMDGPUIntrinsics.td

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} }
// Legacy names for compatibility. // Legacy names for compatibility.
let TargetPrefix = "AMDIL", isTarget = 1 in { let TargetPrefix = "AMDIL", isTarget = 1 in {
def int_AMDIL_clamp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; def int_AMDIL_clamp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
def int_AMDIL_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; def int_AMDIL_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
} }
let TargetPrefix = "TGSI", isTarget = 1 in {
def int_TGSI_lit_z : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],[IntrNoMem]>;
}
include "SIIntrinsics.td" include "SIIntrinsics.td"

lib/Target/AMDGPU/EvergreenInstructions.td

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def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", AMDGPUffbh_u32, VecALU>; def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", AMDGPUffbh_u32, VecALU>;
def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", cttz_zero_undef, VecALU>; def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", cttz_zero_undef, VecALU>;
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>; def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>;
} }
def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
let Pattern = []; let Pattern = [];
let Itinerary = AnyALU; let Itinerary = AnyALU;
} }
def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>;
def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> {
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lib/Target/AMDGPU/R600Instructions.td

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def : Pat< def : Pat<
(fdiv f32:$src0, f32:$src1), (fdiv f32:$src0, f32:$src1),
(MUL_IEEE $src0, (recip_ieee $src1)) (MUL_IEEE $src0, (recip_ieee $src1))
>; >;
def : RcpPat<recip_ieee, f32>; def : RcpPat<recip_ieee, f32>;
} }
class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee>
: Pat <
(int_TGSI_lit_z f32:$src_x, f32:$src_y, f32:$src_w),
(exp_ieee (mul_lit (log_clamped (MAX $src_y, (f32 ZERO))), $src_w, $src_x))
>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// R600 / R700 Instructions // R600 / R700 Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [isR600] in { let Predicates = [isR600] in {
def MUL_LIT_r600 : MUL_LIT_Common<0x0C>; def MUL_LIT_r600 : MUL_LIT_Common<0x0C>;
def MULADD_r600 : MULADD_Common<0x10>; def MULADD_r600 : MULADD_Common<0x10>;
Show All 22 Lineslet Predicates = [isR600] in {
def MULLO_INT_r600 : MULLO_INT_Common<0x73>; def MULLO_INT_r600 : MULLO_INT_Common<0x73>;
def MULHI_INT_r600 : MULHI_INT_Common<0x74>; def MULHI_INT_r600 : MULHI_INT_Common<0x74>;
def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>;
def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>; def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>; defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>; def : POW_Common <LOG_IEEE_r600, EXP_IEEE_r600, MUL>;
def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>; def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>;
def : RsqPat<RECIPSQRT_IEEE_r600, f32>; def : RsqPat<RECIPSQRT_IEEE_r600, f32>;
def R600_ExportSwz : ExportSwzInst { def R600_ExportSwz : ExportSwzInst {
let Word1{20-17} = 0; // BURST_COUNT let Word1{20-17} = 0; // BURST_COUNT
let Word1{21} = eop; let Word1{21} = eop;
let Word1{22} = 0; // VALID_PIXEL_MODE let Word1{22} = 0; // VALID_PIXEL_MODE
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