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AMDGPU: Remove redundant let mayLoad = 1
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Authored by arsenm on Jan 4 2016, 2:13 PM.

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• tstellarAMD
nhaehnle

Summary

This is already set on the SMRD format class.

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arsenm updated this revision to Diff 43923.Jan 4 2016, 2:13 PM

arsenm retitled this revision from to AMDGPU: Remove redundant let mayLoad = 1.

arsenm updated this object.

arsenm added a reviewer: • tstellarAMD.

arsenm added a subscriber: llvm-commits.

Herald added a subscriber: arsenm. · View Herald TranscriptJan 4 2016, 2:13 PM

LGTM

This revision is now accepted and ready to land.Jan 4 2016, 3:45 PM

r256813

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lib/

Target/

AMDGPU/

SIInstructions.td

4 lines

Diff 43923

lib/Target/AMDGPU/SIInstructions.td

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	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//

	defm EXP : EXP_m;			defm EXP : EXP_m;

	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//
	// SMRD Instructions			// SMRD Instructions
	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//

	let mayLoad = 1 in {

	// We are using the SGPR_32 and not the SReg_32 register class for 32-bit			// We are using the SGPR_32 and not the SReg_32 register class for 32-bit
	// SMRD instructions, because the SGPR_32 register class does not include M0			// SMRD instructions, because the SGPR_32 register class does not include M0
	// and writing to M0 from an SMRD instruction will hang the GPU.			// and writing to M0 from an SMRD instruction will hang the GPU.
	defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SGPR_32>;			defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SGPR_32>;
	defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>;			defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>;
	defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>;			defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>;
	defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>;			defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>;
	defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>;			defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>;
	Show All 13 Lines
	defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <			defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
	smrd<0x0b>, "s_buffer_load_dwordx8", SReg_128, SReg_256			smrd<0x0b>, "s_buffer_load_dwordx8", SReg_128, SReg_256
	>;			>;

	defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <			defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
	smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512			smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512
	>;			>;

	} // mayLoad = 1

	//def S_MEMTIME : SMRD_ <0x0000001e, "s_memtime", []>;			//def S_MEMTIME : SMRD_ <0x0000001e, "s_memtime", []>;

	defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv",			defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv",
	int_amdgcn_s_dcache_inv>;			int_amdgcn_s_dcache_inv>;

	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//
	// SOP1 Instructions			// SOP1 Instructions
	//===----------------------------------------------------------------------===//			//===----------------------------------------------------------------------===//
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