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Differential D15763

AMDGPU/SI: Move VI SMEM pattern back into VIInstructions.td
ClosedPublic

Authored by • tstellarAMD on Dec 23 2015, 5:51 PM.

Details

Reviewers
cfang
arsenm
Commits
rG3da5672755d3: AMDGPU/SI: Move VI SMEM pattern back into VIInstructions.td
rL256775: AMDGPU/SI: Move VI SMEM pattern back into VIInstructions.td
Summary

This was accidently moved to CIInstructions.td in r256282

Diff Detail

Repository
rL LLVM

Event Timeline

• tstellarAMD updated this revision to Diff 43571.Dec 23 2015, 5:51 PM
• tstellarAMD retitled this revision from to AMDGPU/SI: Move VI SMEM pattern back into VIInstructions.td.
• tstellarAMD updated this object.
• tstellarAMD added reviewers: arsenm, cfang.
• tstellarAMD added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptDec 23 2015, 5:51 PM
arsenm accepted this revision.Dec 23 2015, 8:38 PM
arsenm edited edge metadata.

LGTM

This revision is now accepted and ready to land.Dec 23 2015, 8:38 PM
Closed by commit rL256775: AMDGPU/SI: Move VI SMEM pattern back into VIInstructions.td (authored by tstellar). · Explain WhyJan 4 2016, 12:26 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
6 lines
9 lines

Diff 43909

llvm/trunk/lib/Target/AMDGPU/CIInstructions.td

Show First 20 Lines • Show All 323 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def useFlatForGlobal : Predicate < def useFlatForGlobal : Predicate <
"Subtarget->useFlatForGlobal() || " "Subtarget->useFlatForGlobal() || "
"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">; "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">;
let Predicates = [useFlatForGlobal] in { let Predicates = [useFlatForGlobal] in {
// 1. Offset as 20bit DWORD immediate
def : Pat <
(SIload_constant v4i32:$sbase, IMM20bit:$offset),
(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
>;
// Patterns for global loads with no offset // Patterns for global loads with no offset
class FlatLoadPat <FLAT inst, SDPatternOperator node, ValueType vt> : Pat < class FlatLoadPat <FLAT inst, SDPatternOperator node, ValueType vt> : Pat <
(vt (node i64:$addr)), (vt (node i64:$addr)),
(inst $addr, 0, 0, 0) (inst $addr, 0, 0, 0)
>; >;
def : FlatLoadPat <FLAT_LOAD_UBYTE, az_extloadi8_global, i32>; def : FlatLoadPat <FLAT_LOAD_UBYTE, az_extloadi8_global, i32>;
def : FlatLoadPat <FLAT_LOAD_SBYTE, sextloadi8_global, i32>; def : FlatLoadPat <FLAT_LOAD_SBYTE, sextloadi8_global, i32>;
Show All 34 Lines

llvm/trunk/lib/Target/AMDGPU/VIInstructions.td

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
def S_DCACHE_WB : SMEM_Inval <0x21, def S_DCACHE_WB : SMEM_Inval <0x21,
"s_dcache_wb", int_amdgcn_s_dcache_wb>; "s_dcache_wb", int_amdgcn_s_dcache_wb>;
def S_DCACHE_WB_VOL : SMEM_Inval <0x23, def S_DCACHE_WB_VOL : SMEM_Inval <0x23,
"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>; "s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
} // End SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI } // End SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI
let Predicates = [isVI] in {
// 1. Offset as 20bit DWORD immediate
def : Pat <
(SIload_constant v4i32:$sbase, IMM20bit:$offset),
(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
>;
} // End Predicates = [isVI]