This is an archive of the discontinued LLVM Phabricator instance.

AMDGPU: Fix getRegisterBitWidth for vectors
ClosedPublic

Authored by arsenm on Dec 21 2015, 11:20 AM.

Reviewers

• tstellarAMD

arsenm retitled this revision from to AMDGPU: Fix getRegisterBitWidth for vectors.

arsenm updated this object.

arsenm added a subscriber: llvm-commits.

LGTM.

This revision is now accepted and ready to land.Dec 23 2015, 8:27 PM

r256362

Path

Size

lib/

Target/

AMDGPU/

4 lines

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines	unsigned AMDGPUTTIImpl::getNumberOfRegisters(bool Vec) {

// Number of VGPRs on SI.		// Number of VGPRs on SI.
if (ST->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)		if (ST->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
return 256;		return 256;

return 4 * 128; // XXX - 4 channels. Should these count as vector instead?		return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
}		}

unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool) { return 32; }		unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool Vector) {
		return Vector ? 0 : 32;
		}

unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {		unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {
// Semi-arbitrary large amount.		// Semi-arbitrary large amount.
return 64;		return 64;
}		}

unsigned AMDGPUTTIImpl::getCFInstrCost(unsigned Opcode) {		unsigned AMDGPUTTIImpl::getCFInstrCost(unsigned Opcode) {
// XXX - For some reason this isn't called for switch.		// XXX - For some reason this isn't called for switch.
▲ Show 20 Lines • Show All 197 Lines • Show Last 20 Lines