AMDGPU: Override getCFInstrCost

[arsenm]

Summary

The default cost was 0 with the assumption that it is predictable.

[• tstellarAMD]

LGTM.

[arsenm]

r255796

lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h

public:
   unsigned getNumberOfRegisters(bool Vector);
   unsigned getRegisterBitWidth(bool Vector);
   unsigned getMaxInterleaveFactor(unsigned VF);
 
   unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) {
     return 0;
   }
 
+  unsigned getCFInstrCost(unsigned Opcode);
+
   int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
   bool isSourceOfDivergence(const Value *V) const;
 
   int getArithmeticInstrCost(
     unsigned Opcode, Type *Ty,
     TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
     TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
     TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
     TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

int AMDGPUTTIImpl::getArithmeticInstrCost(
 
   switch (ISD) {
   default:
     return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
                                          Opd1PropInfo, Opd2PropInfo);
   }
 }
 
+unsigned AMDGPUTTIImpl::getCFInstrCost(unsigned Opcode) {
+  // XXX - For some reason this isn't called for switch.
+  switch (Opcode) {
+  case Instruction::Br:
+  case Instruction::Ret:
+    return 10;
+  default:
+    return BaseT::getCFInstrCost(Opcode);
+  }
+}
 
 int AMDGPUTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
                                       unsigned Index) {
   switch (Opcode) {
   case Instruction::ExtractElement:
     // Dynamic indexing isn't free and is best avoided.
     return Index == ~0u ? 2 : 0;
   default:

test/Analysis/CostModel/AMDGPU/br.ll

+; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
+
+; CHECK: 'test_br_cost'
+; CHECK: estimated cost of 10 for instruction: br i1
+; CHECK: estimated cost of 10 for instruction: br label
+; CHECK: estimated cost of 10 for instruction: ret void
+define void @test_br_cost(i32 addrspace(1)* %out, i32 addrspace(1)* %vaddr, i32 %b) #0 {
+bb0:
+  br i1 undef, label %bb1, label %bb2
+
+bb1:
+  %vec = load i32, i32 addrspace(1)* %vaddr
+  %add = add i32 %vec, %b
+  store i32 %add, i32 addrspace(1)* %out
+  br label %bb2
+
+bb2:
+  ret void
+
+}
+
+; CHECK: 'test_switch_cost'
+; CHECK: Unknown cost for instruction:   switch
+define void @test_switch_cost(i32 %a) #0 {
+entry:
+  switch i32 %a, label %default [
+    i32 0, label %case0
+    i32 1, label %case1
+  ]
+
+case0:
+  store volatile i32 undef, i32 addrspace(1)* undef
+  ret void
+
+case1:
+  store volatile i32 undef, i32 addrspace(1)* undef
+  ret void
+
+default:
+  store volatile i32 undef, i32 addrspace(1)* undef
+  ret void
+
+end:
+  ret void
+}