This is an archive of the discontinued LLVM Phabricator instance.

Differential D15190

[mips][ias] Range check uimm6 operands and fix a bug this revealed.
ClosedPublic

Authored by dsanders on Dec 3 2015, 7:04 AM.

Details

Reviewers
vkalintiris
Commits
rG59d092f883a4: [mips][ias] Range check uimm6 operands and fix a bug this revealed.
rL255015: [mips][ias] Range check uimm6 operands and fix a bug this revealed.
Summary

We don't check the size operand on ext/dext*/ins/dins* yet because the
permitted range depends on the pos argument and we can't check that using
this mechanism.

The bug was that dextu/dinsu accepted 0..31 in the pos operand instead of 32..63.

Diff Detail

Event Timeline

dsanders updated this revision to Diff 41752.Dec 3 2015, 7:04 AM
dsanders retitled this revision from to [mips][ias] Range check uimm6 operands and fix a bug this revealed..
dsanders updated this object.
dsanders added a reviewer: vkalintiris.
dsanders added a subscriber: llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptDec 3 2015, 7:04 AM
dsanders added a child revision: D15226: [mips][ias] Range check uimm8 operands.Dec 4 2015, 3:42 AM
dsanders added a child revision: D15229: [mips][ias] Range check uimm10 operands.Dec 4 2015, 6:19 AM
vkalintiris accepted this revision.Dec 5 2015, 7:26 AM
vkalintiris edited edge metadata.

LGTM. Please, split the error line at MipsAsmParser.cpp because it's too big.

This revision is now accepted and ready to land.Dec 5 2015, 7:26 AM
dsanders closed this revision.Dec 8 2015, 5:52 AM

Revision Contents

PathSize
lib/
Target/
Mips/
AsmParser/
2 lines
4 lines
4 lines
25 lines
126 lines
test/
MC/
Mips/
micromips64r6/
14 lines
2 lines
mips32r2/
14 lines
mips64r2/
42 lines
msa/
28 lines
24 lines

Diff 41752

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 3,641 Lines • ▼ Show 20 Linesbool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_UImm5_0_Report_UImm6: case Match_UImm5_0_Report_UImm6:
// This is used on UImm5 operands that have a corresponding UImm5_32 // This is used on UImm5 operands that have a corresponding UImm5_32
// operand to avoid confusing the user. // operand to avoid confusing the user.
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 6-bit unsigned immediate"); "expected 6-bit unsigned immediate");
case Match_UImm5_Lsl2: case Match_UImm5_Lsl2:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected both 7-bit unsigned immediate and multiple of 4"); "expected both 7-bit unsigned immediate and multiple of 4");
case Match_UImm6_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 6-bit unsigned immediate");
} }
llvm_unreachable("Implement any new match types added!"); llvm_unreachable("Implement any new match types added!");
} }
void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) {
if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex) if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex)
Warning(Loc, "used $at (currently $" + Twine(RegIndex) + Warning(Loc, "used $at (currently $" + Twine(RegIndex) +
▲ Show 20 Lines • Show All 2,526 Lines • Show Last 20 Lines

lib/Target/Mips/MicroMips64r6InstrInfo.td

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Linesclass EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size"); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))]; list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
InstrItinClass Itinerary = II_EXT; InstrItinClass Itinerary = II_EXT;
Format Form = FrmR; Format Form = FrmR;
string BaseOpcode = instr_asm; string BaseOpcode = instr_asm;
} }
class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm6, class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm6,
MipsExt>; MipsExt>;
class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm6, class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
MipsExt>; MipsExt>;
class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm6, class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
MipsExt>; MipsExt>;
class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst { Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst {
dag OutOperandList = (outs GPROpnd:$rd); dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp); dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp"); string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
list<dag> Pattern = []; list<dag> Pattern = [];
Show All 36 Lines

lib/Target/Mips/Mips64InstrInfo.td

Show First 20 Lines • Show All 269 Lines • ▼ Show 20 Lines
def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM; def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>; def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>; def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>; def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32>, EXT_FM<2>;
} }
def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>; def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>; def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32>, EXT_FM<6>;
def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>; def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
let isCodeGenOnly = 1, rs = 0, shamt = 0 in { let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt), def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
"dsll\t$rd, $rt, 32", [], II_DSLL>; "dsll\t$rd, $rt, 32", [], II_DSLL>;
def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt), def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
"sll\t$rd, $rt, 0", [], II_SLL>; "sll\t$rd, $rt, 0", [], II_SLL>;
def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt), def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
▲ Show 20 Lines • Show All 390 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 388 Lines • ▼ Show 20 Linesclass ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],
int Offset = 0> : AsmOperandClass { int Offset = 0> : AsmOperandClass {
let Name = "ConstantUImm" # Bits # "_" # Offset; let Name = "ConstantUImm" # Bits # "_" # Offset;
let RenderMethod = "addConstantUImmOperands<" # Bits # ", " # Offset # ">"; let RenderMethod = "addConstantUImmOperands<" # Bits # ", " # Offset # ">";
let PredicateMethod = "isConstantUImm<" # Bits # ", " # Offset # ">"; let PredicateMethod = "isConstantUImm<" # Bits # ", " # Offset # ">";
let SuperClasses = Supers; let SuperClasses = Supers;
let DiagnosticType = "UImm" # Bits # "_" # Offset; let DiagnosticType = "UImm" # Bits # "_" # Offset;
} }
def ConstantUImm6AsmOperandClass
: ConstantUImmAsmOperandClass<6, []>;
def ConstantUImm5Plus32AsmOperandClass
: ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32>;
def ConstantUImm5Plus32NormalizeAsmOperandClass def ConstantUImm5Plus32NormalizeAsmOperandClass
: ConstantUImmAsmOperandClass<5, [], 32> { : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass], 32> {
let Name = "ConstantUImm5_32_Norm";
// We must also subtract 32 when we render the operand. // We must also subtract 32 when we render the operand.
let RenderMethod = "addConstantUImmOperands<5, 32, -32>"; let RenderMethod = "addConstantUImmOperands<5, 32, -32>";
} }
def ConstantUImm5Lsl2AsmOperandClass : AsmOperandClass { def ConstantUImm5Lsl2AsmOperandClass : AsmOperandClass {
let Name = "UImm5Lsl2"; let Name = "UImm5Lsl2";
let RenderMethod = "addImmOperands"; let RenderMethod = "addImmOperands";
let PredicateMethod = "isScaledUImm<5, 2>"; let PredicateMethod = "isScaledUImm<5, 2>";
let SuperClasses = []; let SuperClasses = [ConstantUImm6AsmOperandClass];
let DiagnosticType = "UImm5_Lsl2"; let DiagnosticType = "UImm5_Lsl2";
} }
def ConstantUImm5ReportUImm6AsmOperandClass def ConstantUImm5ReportUImm6AsmOperandClass
: ConstantUImmAsmOperandClass<5, []> { : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass]> {
let Name = "ConstantUImm5_0_Report_UImm6"; let Name = "ConstantUImm5_0_Report_UImm6";
let DiagnosticType = "UImm5_0_Report_UImm6"; let DiagnosticType = "UImm5_0_Report_UImm6";
} }
def ConstantUImm5AsmOperandClass def ConstantUImm5AsmOperandClass
: ConstantUImmAsmOperandClass<5, []>; : ConstantUImmAsmOperandClass<5, [ConstantUImm6AsmOperandClass]>;
def ConstantUImm4AsmOperandClass def ConstantUImm4AsmOperandClass
: ConstantUImmAsmOperandClass< : ConstantUImmAsmOperandClass<
4, [ConstantUImm5AsmOperandClass, 4, [ConstantUImm5AsmOperandClass,
ConstantUImm5Plus32AsmOperandClass,
ConstantUImm5Plus32NormalizeAsmOperandClass]>; ConstantUImm5Plus32NormalizeAsmOperandClass]>;
def ConstantUImm3AsmOperandClass def ConstantUImm3AsmOperandClass
: ConstantUImmAsmOperandClass<3, [ConstantUImm4AsmOperandClass]>; : ConstantUImmAsmOperandClass<3, [ConstantUImm4AsmOperandClass]>;
def ConstantUImm2Plus1AsmOperandClass def ConstantUImm2Plus1AsmOperandClass
: ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass], 1>; : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass], 1>;
def ConstantUImm2AsmOperandClass def ConstantUImm2AsmOperandClass
: ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass]>; : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass]>;
def ConstantUImm1AsmOperandClass def ConstantUImm1AsmOperandClass
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
// Zero // Zero
def uimmz : Operand<i32> { def uimmz : Operand<i32> {
let PrintMethod = "printUnsignedImm"; let PrintMethod = "printUnsignedImm";
let ParserMatchClass = ConstantImmzAsmOperandClass; let ParserMatchClass = ConstantImmzAsmOperandClass;
} }
// Unsigned Operands // Unsigned Operands
foreach I = {1, 2, 3, 4, 5} in foreach I = {1, 2, 3, 4, 5, 6} in
def uimm # I : Operand<i32> { def uimm # I : Operand<i32> {
let PrintMethod = "printUnsignedImm"; let PrintMethod = "printUnsignedImm";
let ParserMatchClass = let ParserMatchClass =
!cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass"); !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
} }
def uimm2_plus1 : Operand<i32> { def uimm2_plus1 : Operand<i32> {
let PrintMethod = "printUnsignedImm"; let PrintMethod = "printUnsignedImm";
let EncoderMethod = "getUImmWithOffsetEncoding<2, 1>"; let EncoderMethod = "getUImmWithOffsetEncoding<2, 1>";
let DecoderMethod = "DecodeUImmWithOffset<2, 1>"; let DecoderMethod = "DecodeUImmWithOffset<2, 1>";
let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass; let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass;
} }
def uimm5_plus32 : Operand<i32> {
let PrintMethod = "printUnsignedImm";
let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass;
}
def uimm5_plus32_normalize : Operand<i32> { def uimm5_plus32_normalize : Operand<i32> {
let PrintMethod = "printUnsignedImm"; let PrintMethod = "printUnsignedImm";
let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass;
} }
def uimm5_lsl2 : Operand<OtherVT> { def uimm5_lsl2 : Operand<OtherVT> {
let EncoderMethod = "getUImm5Lsl2Encoding"; let EncoderMethod = "getUImm5Lsl2Encoding";
let DecoderMethod = "DecodeUImm5lsl2"; let DecoderMethod = "DecodeUImm5lsl2";
Show All 14 Lines
// Like uimm5_64 but reports a less confusing error for 32-63 when // Like uimm5_64 but reports a less confusing error for 32-63 when
// an instruction alias permits that. // an instruction alias permits that.
def uimm5_64_report_uimm6 : Operand<i64> { def uimm5_64_report_uimm6 : Operand<i64> {
let PrintMethod = "printUnsignedImm"; let PrintMethod = "printUnsignedImm";
let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass;
} }
def uimm6 : Operand<i32> {
let PrintMethod = "printUnsignedImm";
}
def uimm16 : Operand<i32> { def uimm16 : Operand<i32> {
let PrintMethod = "printUnsignedImm"; let PrintMethod = "printUnsignedImm";
} }
def pcrel16 : Operand<i32> { def pcrel16 : Operand<i32> {
} }
def MipsMemAsmOperand : AsmOperandClass { def MipsMemAsmOperand : AsmOperandClass {
▲ Show 20 Lines • Show All 1,705 Lines • Show Last 20 Lines

lib/Target/Mips/MipsMSAInstrInfo.td

Show First 20 Lines • Show All 1,171 Lines • ▼ Show 20 Linesclass MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
InstrItinClass itin = NoItinerary> { InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd); dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
InstrItinClass Itinerary = itin; InstrItinClass Itinerary = itin;
} }
// This class is deprecated and will be removed soon. class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, uimm3:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
InstrItinClass Itinerary = itin;
}
// This class is deprecated and will be removed soon.
class MSA_BIT_H_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, uimm4:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
InstrItinClass Itinerary = itin;
}
// This class is deprecated and will be removed soon.
class MSA_BIT_W_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, uimm5:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
InstrItinClass Itinerary = itin;
}
// This class is deprecated and will be removed soon.
class MSA_BIT_D_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> { InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd); dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, uimm6:$m); dag InOperandList = (ins ROWS:$ws, ImmOp:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))]; list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
InstrItinClass Itinerary = itin; InstrItinClass Itinerary = itin;
} }
class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
ComplexPattern Mask, RegisterOperand ROWD, ComplexPattern Mask, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> { InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd); dag OutOperandList = (outs ROWD:$wd);
▲ Show 20 Lines • Show All 268 Lines • ▼ Show 20 Linesclass MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs), MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs),
[(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
ROIdx:$n))]> { ROIdx:$n))]> {
bit usesCustomInserter = 1; bit usesCustomInserter = 1;
string Constraints = "$wd = $wd_in"; string Constraints = "$wd = $wd_in";
} }
class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD, Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> { InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd); dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws, uimmz:$n2); dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2);
string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
immZExt6:$n, Imm:$n,
ROWS:$ws, ROWS:$ws,
immz:$n2))]; immz:$n2))];
InstrItinClass Itinerary = itin; InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in"; string Constraints = "$wd = $wd_in";
} }
class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD, RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
▲ Show 20 Lines • Show All 802 Lines • ▼ Show 20 Lines
class INSERT_D_VIDX64_PSEUDO_DESC : class INSERT_D_VIDX64_PSEUDO_DESC :
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>; MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>;
class INSERT_FW_VIDX64_PSEUDO_DESC : class INSERT_FW_VIDX64_PSEUDO_DESC :
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>; MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>;
class INSERT_FD_VIDX64_PSEUDO_DESC : class INSERT_FD_VIDX64_PSEUDO_DESC :
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>; MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>;
class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, immZExt4,
MSA128BOpnd>; MSA128BOpnd>;
class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, immZExt3,
MSA128HOpnd>; MSA128HOpnd>;
class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, immZExt2,
MSA128WOpnd>; MSA128WOpnd>;
class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, immZExt1,
MSA128DOpnd>; MSA128DOpnd>;
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD, ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
InstrItinClass itin = NoItinerary> { InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd); dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins MemOpnd:$addr); dag InOperandList = (ins MemOpnd:$addr);
▲ Show 20 Lines • Show All 192 Lines • ▼ Show 20 Lines
class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>; class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>; class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>; class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3,
MSA128BOpnd>; immZExt3, MSA128BOpnd>;
class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4,
MSA128HOpnd>; immZExt4, MSA128HOpnd>;
class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5,
MSA128WOpnd>; immZExt5, MSA128WOpnd>;
class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6,
MSA128DOpnd>; immZExt6, MSA128DOpnd>;
class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3,
MSA128BOpnd>; immZExt3, MSA128BOpnd>;
class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4,
MSA128HOpnd>; immZExt4, MSA128HOpnd>;
class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5,
MSA128WOpnd>; immZExt5, MSA128WOpnd>;
class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6,
MSA128DOpnd>; immZExt6, MSA128DOpnd>;
class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
MSA128DOpnd>; MSA128DOpnd>;
class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b, class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3,
MSA128BOpnd>; immZExt3, MSA128BOpnd>;
class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h, class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4,
MSA128HOpnd>; immZExt4, MSA128HOpnd>;
class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w, class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5,
MSA128WOpnd>; immZExt5, MSA128WOpnd>;
class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d, class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6,
MSA128DOpnd>; immZExt6, MSA128DOpnd>;
class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
MSA128BOpnd>; MSA128BOpnd>;
class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
MSA128HOpnd>; MSA128HOpnd>;
class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
MSA128WOpnd>; MSA128WOpnd>;
class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
MSA128DOpnd>; MSA128DOpnd>;
class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b, class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3,
MSA128BOpnd>; immZExt3, MSA128BOpnd>;
class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h, class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4,
MSA128HOpnd>; immZExt4, MSA128HOpnd>;
class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w, class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5,
MSA128WOpnd>; immZExt5, MSA128WOpnd>;
class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d, class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6,
MSA128DOpnd>; immZExt6, MSA128DOpnd>;
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD, ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
InstrItinClass itin = NoItinerary> { InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs); dag OutOperandList = (outs);
dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
▲ Show 20 Lines • Show All 1,257 Lines • Show Last 20 Lines

test/MC/Mips/micromips64r6/invalid.s

Show All 12 Lines# RUN: FileCheck %s < %t1
beqzc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction beqzc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
beqzc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address beqzc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
beqzc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range beqzc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bnezc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction bnezc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
bnezc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address bnezc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
# FIXME: Check size on dext*
dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
dextm $2, $3, 32, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
dextu $2, $3, 31, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
dextu $2, $3, 64, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
# FIXME: Check size on dins*
dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
dins $2, $3, 64, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
dinsm $2, $3, -1, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
dinsm $2, $3, 32, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
dinsu $2, $3, 31, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
dinsu $2, $3, 64, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
dalign $4, $2, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate dalign $4, $2, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
dalign $4, $2, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate dalign $4, $2, $3, 8 # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
lbu16 $9, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lbu16 $9, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

test/MC/Mips/micromips64r6/valid.s

Show All 13 Linesa:
bc16 132 # CHECK: bc16 132 # encoding: [0xcc,0x42] bc16 132 # CHECK: bc16 132 # encoding: [0xcc,0x42]
beqzc16 $6, 20 # CHECK: beqzc16 $6, 20 # encoding: [0x8f,0x0a] beqzc16 $6, 20 # CHECK: beqzc16 $6, 20 # encoding: [0x8f,0x0a]
bnezc16 $6, 20 # CHECK: bnezc16 $6, 20 # encoding: [0xaf,0x0a] bnezc16 $6, 20 # CHECK: bnezc16 $6, 20 # encoding: [0xaf,0x0a]
daui $3, $4, 5 # CHECK: daui $3, $4, 5 # encoding: [0xf0,0x64,0x00,0x05] daui $3, $4, 5 # CHECK: daui $3, $4, 5 # encoding: [0xf0,0x64,0x00,0x05]
dahi $3, 4 # CHECK: dahi $3, 4 # encoding: [0x42,0x23,0x00,0x04] dahi $3, 4 # CHECK: dahi $3, 4 # encoding: [0x42,0x23,0x00,0x04]
dati $3, 4 # CHECK: dati $3, 4 # encoding: [0x42,0x03,0x00,0x04] dati $3, 4 # CHECK: dati $3, 4 # encoding: [0x42,0x03,0x00,0x04]
dext $9, $6, 3, 7 # CHECK: dext $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xec] dext $9, $6, 3, 7 # CHECK: dext $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xec]
dextm $9, $6, 3, 7 # CHECK: dextm $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xe4] dextm $9, $6, 3, 7 # CHECK: dextm $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xe4]
dextu $9, $6, 3, 7 # CHECK: dextu $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xd4] dextu $9, $6, 35, 7 # CHECK: dextu $9, $6, 35, 7 # encoding: [0x59,0x26,0x30,0xd4]
dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c] dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c]
lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88] lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66] lw $3, 24($sp) # CHECK: lw $3, 24($sp) # encoding: [0x48,0x66]
lw16 $4, 8($17) # CHECK: lw16 $4, 8($17) # encoding: [0x6a,0x12] lw16 $4, 8($17) # CHECK: lw16 $4, 8($17) # encoding: [0x6a,0x12]
lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82] lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94] lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f] lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0x64,0x29,0x18] ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0x64,0x29,0x18]
▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines

test/MC/Mips/mips32r2/invalid.s

# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. # Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
# invalid set of operands or operand's restrictions not met). # invalid set of operands or operand's restrictions not met).
# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 2>%t1 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.text .text
.set noreorder .set noreorder
cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
# FIXME: Check size on ext
ext $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
ext $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
# FIXME: Check size on ins
ins $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
sll $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
sll $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
srl $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
srl $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
sra $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
sra $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
rotr $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
rotr $2, $3, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate

test/MC/Mips/mips64r2/invalid.s

# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. # Instructions that are valid for the current ISA but should be rejected by the assembler (e.g.
# invalid set of operands or operand's restrictions not met). # invalid set of operands or operand's restrictions not met).
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r2 2>%t1 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r2 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.text .text
.set noreorder .set noreorder
cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
# FIXME: Check size on dext*
dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dextm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
dextm $2, $3, 32, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
dextu $2, $3, 31, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
dextu $2, $3, 64, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
# FIXME: Check size on dins*
dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dins $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dinsm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
dinsm $2, $3, 32, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate
dinsu $2, $3, 31, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
dinsu $2, $3, 64, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63
drotr $2, $3, -1 # CHECK: :[[@LINE]]:23: error: expected 6-bit unsigned immediate
drotr $2, $3, 64 # CHECK: :[[@LINE]]:23: error: expected 6-bit unsigned immediate
drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate drotr32 $2, $3, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate drotr32 $2, $3, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
dsll $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dsll $2, $3, 64 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dsll32 $2, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
dsll32 $2, $3, 32 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
dsrl $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dsrl $2, $3, 64 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dsrl32 $2, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
dsrl32 $2, $3, 64 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
dsra $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dsra $2, $3, 64 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate
dsra32 $2, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
dsra32 $2, $3, 64 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
# FIXME: Check size on ext
ext $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
ext $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
# FIXME: Check size on ins
ins $2, $3, -1, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
sll $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
sll $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
srl $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
srl $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
sra $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
sra $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
rotr $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate
rotr $2, $3, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate

test/MC/Mips/msa/invalid-64.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips64r2 -mattr=+msa \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips64r2 -mattr=+msa \
# RUN: -show-encoding 2>%t1 # RUN: -show-encoding 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
dlsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 dlsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
dlsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 dlsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
insve.b $w25[-1], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
insve.b $w25[16], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
insve.h $w24[-1], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
insve.h $w24[8], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
insve.w $w0[-1], $w13[0] # CHECK: :[[@LINE]]:17: error: expected 2-bit unsigned immediate
insve.w $w0[4], $w13[0] # CHECK: :[[@LINE]]:17: error: expected 2-bit unsigned immediate
insve.d $w3[-1], $w18[0] # CHECK: :[[@LINE]]:17: error: expected 1-bit unsigned immediate
insve.d $w3[2], $w18[0] # CHECK: :[[@LINE]]:17: error: expected 1-bit unsigned immediate
insve.b $w25[3], $w9[1] # CHECK: :[[@LINE]]:26: error: expected '0' insve.b $w25[3], $w9[1] # CHECK: :[[@LINE]]:26: error: expected '0'
insve.h $w24[2], $w2[1] # CHECK: :[[@LINE]]:26: error: expected '0' insve.h $w24[2], $w2[1] # CHECK: :[[@LINE]]:26: error: expected '0'
insve.w $w0[2], $w13[1] # CHECK: :[[@LINE]]:26: error: expected '0' insve.w $w0[2], $w13[1] # CHECK: :[[@LINE]]:26: error: expected '0'
insve.d $w3[0], $w18[1] # CHECK: :[[@LINE]]:26: error: expected '0' insve.d $w3[0], $w18[1] # CHECK: :[[@LINE]]:26: error: expected '0'
lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
sat_s.b $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate sat_s.b $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate
sat_s.b $w31, $w31, 8 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate sat_s.b $w31, $w31, 8 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate
sat_s.h $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate sat_s.h $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate
sat_s.h $w31, $w31, 16 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate sat_s.h $w31, $w31, 16 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate
sat_s.w $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
sat_s.w $w31, $w31, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
sat_s.d $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 6-bit unsigned immediate
sat_s.d $w31, $w31, 64 # CHECK: :[[@LINE]]:25: error: expected 6-bit unsigned immediate
sat_u.b $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate sat_u.b $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate
sat_u.b $w31, $w31, 8 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate sat_u.b $w31, $w31, 8 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate
sat_u.h $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate sat_u.h $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate
sat_u.h $w31, $w31, 16 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate sat_u.h $w31, $w31, 16 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate
sat_u.w $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
sat_u.w $w31, $w31, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
sat_u.d $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 6-bit unsigned immediate
sat_u.d $w31, $w31, 64 # CHECK: :[[@LINE]]:25: error: expected 6-bit unsigned immediate
sldi.b $w0, $w29[-1] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate sldi.b $w0, $w29[-1] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
sldi.b $w0, $w29[16] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate sldi.b $w0, $w29[16] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
sldi.d $w4, $w12[-1] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate sldi.d $w4, $w12[-1] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
sldi.d $w4, $w12[2] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate sldi.d $w4, $w12[2] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
sldi.h $w8, $w17[-1] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate sldi.h $w8, $w17[-1] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
sldi.h $w8, $w17[8] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate sldi.h $w8, $w17[8] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
sldi.w $w20, $w27[-1] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate sldi.w $w20, $w27[-1] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate
sldi.w $w20, $w27[4] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate sldi.w $w20, $w27[4] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate
srari.b $w5, $w25, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate srari.b $w5, $w25, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
srari.b $w5, $w25, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate srari.b $w5, $w25, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
srari.h $w5, $w25, -1 # CHECK: :[[@LINE]]:24: error: expected 4-bit unsigned immediate
srari.h $w5, $w25, 16 # CHECK: :[[@LINE]]:24: error: expected 4-bit unsigned immediate
srari.w $w5, $w25, -1 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
srari.w $w5, $w25, 32 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
srari.d $w5, $w25, -1 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
srari.d $w5, $w25, 64 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
srlri.b $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate srlri.b $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
srlri.b $w18, $w3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate srlri.b $w18, $w3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
srlri.h $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 4-bit unsigned immediate
srlri.h $w18, $w3, 16 # CHECK: :[[@LINE]]:24: error: expected 4-bit unsigned immediate
srlri.w $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
srlri.w $w18, $w3, 32 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
srlri.d $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
srlri.d $w18, $w3, 64 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate

test/MC/Mips/msa/invalid.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa \
# RUN: -show-encoding 2>%t1 # RUN: -show-encoding 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
insve.b $w25[-1], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
insve.b $w25[16], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate
insve.h $w24[-1], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
insve.h $w24[8], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
insve.w $w0[-1], $w13[0] # CHECK: :[[@LINE]]:17: error: expected 2-bit unsigned immediate
insve.w $w0[4], $w13[0] # CHECK: :[[@LINE]]:17: error: expected 2-bit unsigned immediate
insve.d $w3[-1], $w18[0] # CHECK: :[[@LINE]]:17: error: expected 1-bit unsigned immediate
insve.d $w3[2], $w18[0] # CHECK: :[[@LINE]]:17: error: expected 1-bit unsigned immediate
insve.b $w25[3], $w9[1] # CHECK: :[[@LINE]]:26: error: expected '0' insve.b $w25[3], $w9[1] # CHECK: :[[@LINE]]:26: error: expected '0'
insve.h $w24[2], $w2[1] # CHECK: :[[@LINE]]:26: error: expected '0' insve.h $w24[2], $w2[1] # CHECK: :[[@LINE]]:26: error: expected '0'
insve.w $w0[2], $w13[1] # CHECK: :[[@LINE]]:26: error: expected '0' insve.w $w0[2], $w13[1] # CHECK: :[[@LINE]]:26: error: expected '0'
insve.d $w3[0], $w18[1] # CHECK: :[[@LINE]]:26: error: expected '0' insve.d $w3[0], $w18[1] # CHECK: :[[@LINE]]:26: error: expected '0'
lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4
sat_s.b $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate sat_s.b $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate
sat_s.b $w31, $w31, 8 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate sat_s.b $w31, $w31, 8 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate
sat_s.h $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate sat_s.h $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate
sat_s.h $w31, $w31, 16 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate sat_s.h $w31, $w31, 16 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate
sat_s.w $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate sat_s.w $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
sat_s.w $w31, $w31, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate sat_s.w $w31, $w31, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
sat_s.d $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 6-bit unsigned immediate
sat_s.d $w31, $w31, 64 # CHECK: :[[@LINE]]:25: error: expected 6-bit unsigned immediate
sat_u.b $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate sat_u.b $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate
sat_u.b $w31, $w31, 8 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate sat_u.b $w31, $w31, 8 # CHECK: :[[@LINE]]:25: error: expected 3-bit unsigned immediate
sat_u.h $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate sat_u.h $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate
sat_u.h $w31, $w31, 16 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate sat_u.h $w31, $w31, 16 # CHECK: :[[@LINE]]:25: error: expected 4-bit unsigned immediate
sat_u.w $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate sat_u.w $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
sat_u.w $w31, $w31, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate sat_u.w $w31, $w31, 32 # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
sat_u.d $w31, $w31, -1 # CHECK: :[[@LINE]]:25: error: expected 6-bit unsigned immediate
sat_u.d $w31, $w31, 64 # CHECK: :[[@LINE]]:25: error: expected 6-bit unsigned immediate
sldi.b $w0, $w29[-1] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate sldi.b $w0, $w29[-1] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
sldi.b $w0, $w29[16] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate sldi.b $w0, $w29[16] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate
sldi.d $w4, $w12[-1] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate sldi.d $w4, $w12[-1] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
sldi.d $w4, $w12[2] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate sldi.d $w4, $w12[2] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate
sldi.h $w8, $w17[-1] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate sldi.h $w8, $w17[-1] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
sldi.h $w8, $w17[8] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate sldi.h $w8, $w17[8] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate
sldi.w $w20, $w27[-1] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate sldi.w $w20, $w27[-1] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate
sldi.w $w20, $w27[4] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate sldi.w $w20, $w27[4] # CHECK: :[[@LINE]]:23: error: expected 2-bit unsigned immediate
srari.b $w5, $w25, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate srari.b $w5, $w25, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
srari.b $w5, $w25, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate srari.b $w5, $w25, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
srari.h $w5, $w25, -1 # CHECK: :[[@LINE]]:24: error: expected 4-bit unsigned immediate
srari.h $w5, $w25, 16 # CHECK: :[[@LINE]]:24: error: expected 4-bit unsigned immediate
srari.w $w5, $w25, -1 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
srari.w $w5, $w25, 32 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
srari.d $w5, $w25, -1 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
srari.d $w5, $w25, 64 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
srlri.b $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate srlri.b $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
srlri.b $w18, $w3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate srlri.b $w18, $w3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
srlri.h $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 4-bit unsigned immediate
srlri.h $w18, $w3, 16 # CHECK: :[[@LINE]]:24: error: expected 4-bit unsigned immediate
srlri.w $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
srlri.w $w18, $w3, 32 # CHECK: :[[@LINE]]:24: error: expected 5-bit unsigned immediate
srlri.d $w18, $w3, -1 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate
srlri.d $w18, $w3, 64 # CHECK: :[[@LINE]]:24: error: expected 6-bit unsigned immediate