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Differential D15128

AMDGPU: Implement isNoopAddrSpaceCast
ClosedPublic

Authored by arsenm on Dec 1 2015, 2:04 PM.

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Reviewers
• tstellarAMD

Diff Detail

Event Timeline

arsenm updated this revision to Diff 41561.Dec 1 2015, 2:04 PM
arsenm retitled this revision from to AMDGPU: Implement isNoopAddrSpaceCast.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptDec 1 2015, 2:04 PM
• tstellarAMD accepted this revision.Dec 1 2015, 2:23 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Dec 1 2015, 2:23 PM
arsenm closed this revision.Dec 1 2015, 3:07 PM

r254468

Revision Contents

PathSize
lib/
Target/
AMDGPU/
2 lines
11 lines
test/
CodeGen/
AMDGPU/
66 lines

Diff 41561

lib/Target/AMDGPU/SIISelLowering.h

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
bool *IsFast) const override; bool *IsFast) const override;
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
unsigned SrcAlign, bool IsMemset, unsigned SrcAlign, bool IsMemset,
bool ZeroMemset, bool ZeroMemset,
bool MemcpyStrSrc, bool MemcpyStrSrc,
MachineFunction &MF) const override; MachineFunction &MF) const override;
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
TargetLoweringBase::LegalizeTypeAction TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(EVT VT) const override; getPreferredVectorAction(EVT VT) const override;
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override; Type *Ty) const override;
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool isVarArg, bool isVarArg,
Show All 37 Lines

lib/Target/AMDGPU/SIISelLowering.cpp

Show First 20 Lines • Show All 486 Lines • ▼ Show 20 LinesEVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
if (Size >= 8 && DstAlign >= 4) if (Size >= 8 && DstAlign >= 4)
return MVT::v2i32; return MVT::v2i32;
// Use the default. // Use the default.
return MVT::Other; return MVT::Other;
} }
static bool isFlatGlobalAddrSpace(unsigned AS) {
return AS == AMDGPUAS::GLOBAL_ADDRESS ||
AS == AMDGPUAS::FLAT_ADDRESS ||
AS == AMDGPUAS::CONSTANT_ADDRESS;
}
bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
unsigned DestAS) const {
return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
}
TargetLoweringBase::LegalizeTypeAction TargetLoweringBase::LegalizeTypeAction
SITargetLowering::getPreferredVectorAction(EVT VT) const { SITargetLowering::getPreferredVectorAction(EVT VT) const {
if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16)) if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
return TypeSplitVector; return TypeSplitVector;
return TargetLoweringBase::getPreferredVectorAction(VT); return TargetLoweringBase::getPreferredVectorAction(VT);
} }
▲ Show 20 Lines • Show All 1,952 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll

Show All 24 Lines
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32 addrspace(4)* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_sink_noop_addrspacecast_flat_to_global_i32(
; OPT: getelementptr i32, i32 addrspace(4)* %out,
; OPT-CI-NOT: getelementptr
; OPT: br i1
; OPT-CI: ptrtoint
; OPT-CI: add
; OPT-CI: inttoptr
; OPT: br label
; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_global_i32:
; CI: buffer_load_dword {{v[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:28
define void @test_sink_noop_addrspacecast_flat_to_global_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) {
entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7
%cast = addrspacecast i32 addrspace(4)* %in.gep to i32 addrspace(1)*
%tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %endif, label %if
if:
%tmp1 = load i32, i32 addrspace(1)* %cast
br label %endif
endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep
br label %done
done:
ret void
}
; OPT-LABEL: @test_sink_noop_addrspacecast_flat_to_constant_i32(
; OPT: getelementptr i32, i32 addrspace(4)* %out,
; OPT-CI-NOT: getelementptr
; OPT: br i1
; OPT-CI: ptrtoint
; OPT-CI: add
; OPT-CI: inttoptr
; OPT: br label
; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_constant_i32:
; CI: s_load_dword {{s[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
define void @test_sink_noop_addrspacecast_flat_to_constant_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) {
entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7
%cast = addrspacecast i32 addrspace(4)* %in.gep to i32 addrspace(2)*
%tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %endif, label %if
if:
%tmp1 = load i32, i32 addrspace(2)* %cast
br label %endif
endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep
br label %done
done:
ret void
}