[TableGen] Fix bug in printing namespace for register altname indices in AsmWriterEmitter

[asb]

Summary

AsmWriterEmitter will generate a getRegisterName function with an alternate register name index as its second argument if the target makes use of them. The enum of these values is generated in RegisterInfoEmitter. The getRegisterName generator would assume the namespace could always be found by reading index 1 of the list of AltNameIndices, but this will fail if this list is sorted such that the NoRegAltName is at index 1. Because this list is sorted by record name (in CodeGenTarget::ReadRegAltNameIndices), you only run in to problems if your MyTargetRegisterInfo.td defines a single RegAltNameIndex that sorts lexically before NoRegAltName.

i.e. if a target has something like def AnAltNameIndex : RegAltNameIndex and defines RegAltNameIndices for some registers then without this patch, AsmWriterEmitter will generate references to ::AnAltNameIndex and ::NoRegAltName.

Adding Jakob Oleson (TableGen code owner) and Jim Grosbach (original author of the RegAltName code) as reviewers. This patch is relevant to D14994, but the two patches are independent.

Patch by Alex Bradbury

[asb]

Apologies, the previous patch missed an uncommitted fix.

[hfinkel]

Seems to make sense, reading the namespace name from the first register def should be a reliable way to get it. LGTM.

[asb]

In D15044#307555, @hfinkel wrote:

Seems to make sense, reading the namespace name from the first register def should be a reliable way to get it. LGTM.

Thanks for reviewing Hal, could you commit please? I've just checked the patch applies cleanly to rL255331, with all tests of course still passing.

[hfinkel]

r255344.

utils/TableGen/AsmWriterEmitter.cpp

 }
 
 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
   Record *AsmWriter = Target.getAsmWriter();
   std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
   const auto &Registers = Target.getRegBank().getRegisters();
   std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
   bool hasAltNames = AltNameIndices.size() > 1;
+  std::string Namespace =
+      Registers.front().TheDef->getValueAsString("Namespace");
 
   O <<
   "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
   "/// from the register set description.  This returns the assembler name\n"
   "/// for the specified register.\n"
   "const char *" << Target.getName() << ClassName << "::";
   if (hasAltNames)
     O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n";
   else
     O << "getRegisterName(unsigned RegNo) {\n";
   O << "  assert(RegNo && RegNo < " << (Registers.size()+1)
     << " && \"Invalid register number!\");\n"
     << "\n";
 
   if (hasAltNames) {
     for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i)
       emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers);
   } else
     emitRegisterNameString(O, "", Registers);
 
   if (hasAltNames) {
     O << "  switch(AltIdx) {\n"
       << "  default: llvm_unreachable(\"Invalid register alt name index!\");\n";
     for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {
-      std::string Namespace = AltNameIndices[1]->getValueAsString("Namespace");
       std::string AltName(AltNameIndices[i]->getName());
-      O << "  case " << Namespace << "::" << AltName << ":\n"
+      std::string Prefix = !Namespace.empty() ? Namespace + "::" : "";
+      O << "  case " << Prefix << AltName << ":\n"
         << "    assert(*(AsmStrs" << AltName << "+RegAsmOffset"
         << AltName << "[RegNo-1]) &&\n"
         << "           \"Invalid alt name index for register!\");\n"
         << "    return AsmStrs" << AltName << "+RegAsmOffset"
         << AltName << "[RegNo-1];\n";
     }
     O << "  }\n";
   } else {