AMDGPU: Disallow s[102:103] on VI in assembler

[• tstellarAMD]

LGTM.

[arsenm]

r252142

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 };
 
 class AMDGPUAsmParser : public MCTargetAsmParser {
   MCSubtargetInfo &STI;
   const MCInstrInfo &MII;
   MCAsmParser &Parser;
 
   unsigned ForcedEncodingSize;
+
+  bool isVI() const {
+    return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
+  }
+
+  bool hasSGPR102_SGPR103() const {
+    return !isVI();
+  }
+
   /// @name Auto-generated Match Functions
   /// {
 
 #define GET_ASSEMBLER_HEADER
 #include "AMDGPUGenAsmMatcher.inc"
 
   /// }
 
 private:
   bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);
   bool ParseDirectiveHSACodeObjectVersion();
   bool ParseDirectiveHSACodeObjectISA();
   bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
   bool ParseDirectiveAMDKernelCodeT();
   bool ParseSectionDirectiveHSAText();
+  bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const;
 
 public:
 public:
   enum AMDGPUMatchResultTy {
     Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY
   };
 
   AMDGPUAsmParser(MCSubtargetInfo &STI, MCAsmParser &_Parser,
                const MCInstrInfo &MII,
                const MCTargetOptions &Options)
       : MCTargetAsmParser(Options), STI(STI), MII(MII), Parser(_Parser),
-        ForcedEncodingSize(0){
+        ForcedEncodingSize(0) {
 
     if (STI.getFeatureBits().none()) {
       // Set default features.
       STI.ToggleFeature("SOUTHERN_ISLANDS");
     }
 
     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
   }
bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
   if (RCID == -1)
     return true;
 
   const MCRegisterClass RC = TRI->getRegClass(RCID);
   if (RegIndexInClass >= RC.getNumRegs())
     return true;
 
   RegNo = RC.getRegister(RegIndexInClass);
-  return false;
+  return !subtargetHasRegister(*TRI, RegNo);
 }
 
 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
 
   uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
 
   if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) ||
       (getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)))
if (IDVal == ".amd_kernel_code_t")
     return ParseDirectiveAMDKernelCodeT();
 
   if (IDVal == ".hsatext" || IDVal == ".text")
     return ParseSectionDirectiveHSAText();
 
   return true;
 }
 
+bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
+                                           unsigned RegNo) const {
+  if (!isVI())
+    return true;
+
+  // VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that
+  // SI/CI have.
+  for (MCRegAliasIterator R(AMDGPU::SGPR102_SGPR103, &MRI, true);
+       R.isValid(); ++R) {
+    if (*R == RegNo)
+      return false;
+  }
+
+  return true;
+}
+
 static bool operandsHaveModifiers(const OperandVector &Operands) {
 
   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
     const AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]);
     if (Op.isRegKind() && Op.hasModifiers())
       return true;
     if (Op.isImm() && (Op.getImmTy() == AMDGPUOperand::ImmTyOMod ||
                        Op.getImmTy() == AMDGPUOperand::ImmTyClamp))

test/MC/AMDGPU/smrd-err.s

+// RUN: llvm-mc -arch=amdgcn -mcpu=tahiti %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
+
+s_load_dwordx4 s[100:103], s[2:3], s4
+// VI: error: invalid operand for instruction
+// SI: s_load_dwordx4 s[100:103], s[2:3], s4
+
+
+s_load_dwordx8 s[96:103], s[2:3], s4
+// VI: error: invalid operand for instruction
+// SI:  s_load_dwordx8 s[96:103], s[2:3], s4
+
+s_load_dwordx16 s[88:103], s[2:3], s4
+// VI: error: invalid operand for instruction
+// SI: s_load_dwordx16 s[88:103], s[2:3], s4

test/MC/AMDGPU/sop1-err.s

-// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
 
 s_mov_b32 v1, s2
-// CHECK: error: invalid operand for instruction
+// GCN: error: invalid operand for instruction
 
 s_mov_b32 s1, v0
-// CHECK: error: invalid operand for instruction
+// GCN: error: invalid operand for instruction
 
 s_mov_b32 s[1:2], s0
-// CHECK: error: invalid operand for instruction
+// GCN: error: invalid operand for instruction
 
 s_mov_b32 s0, s[1:2]
-// CHECK: error: invalid operand for instruction
+// GCN: error: invalid operand for instruction
 
 s_mov_b32 s220, s0
-// CHECK: error: invalid operand for instruction
+// GCN: error: invalid operand for instruction
 
 s_mov_b32 s0, s220
-// CHECK: error: invalid operand for instruction
+// GCN: error: invalid operand for instruction
 
 s_mov_b64 s1, s[0:1]
-// CHECK: error: invalid operand for instruction
+// GCN: error: invalid operand for instruction
 
 s_mov_b64 s[0:1], s1
-// CHECK: error: invalid operand for instruction
+// GCN: error: invalid operand for instruction
 
 // Immediate greater than 32-bits
 s_mov_b32 s1, 0xfffffffff
-// CHECK: error: invalid immediate: only 32-bit values are legal
+// GCN: error: invalid immediate: only 32-bit values are legal
 
 // Immediate greater than 32-bits
 s_mov_b64 s[0:1], 0xfffffffff
-// CHECK: error: invalid immediate: only 32-bit values are legal
+// GCN: error: invalid immediate: only 32-bit values are legal
 
 s_mov_b64 s[0:1], 0xfffffffff
-// CHECK: error: invalid immediate: only 32-bit values are legal
+// GCN: error: invalid immediate: only 32-bit values are legal
 
 s_mov_b64 s[0:1], 0xfffffffff
-// CHECK: error: invalid immediate: only 32-bit values are legal
+// GCN: error: invalid immediate: only 32-bit values are legal
 
 s_mov_b64 s[0:1], 0x0000000200000000
-// CHECK: error: invalid immediate: only 32-bit values are legal
+// GCN: error: invalid immediate: only 32-bit values are legal
 
 // Out of range register
 s_mov_b32 s
+
+s_mov_b32 s102, 1
+// VI: error: invalid operand for instruction
+// SI-NOT: error
+
+s_mov_b32 s103, 1
+// VI: error: invalid operand for instruction
+// SI-NOT: error
+
+s_mov_b64 s[102:103], -1
+// VI: error: invalid operand for instruction
+// SI-NOT: error